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Ming-Tsung Chen
Ming-Tsung Chen, Hsin-Chu Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20100073671 | ALIGNMENT MARK AND DEFECT INSPECTION METHOD - A defect inspection method is disclosed. A first type defect inspection system is used to perform a first defect inspection by aligning to an alignment mark on a wafer as a reference point for the first defect inspection. A fabrication process is performed on the wafer thereafter, and a second defect inspection is performed by using a second type defect inspection system to align the alignment mark on the wafer as the reference point for the second defect inspection. | 03-25-2010 |
| 20100213554 | GATE STRUCTURE AND METHOD FOR TRIMMING SPACERS - A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer. | 08-26-2010 |
| 20100327451 | ALIGNMENT MARK - An alignment mark for defect inspection is disclosed. The alignment mark includes: a semiconductor substrate; a first type well disposed in the semiconductor substrate; a second type doping region disposed in the first type well; a dielectric layer disposed on the semiconductor substrate to cover the first type well and the second type doping region; and a plurality of conductive plugs formed in the dielectric layer for connecting to the second type doping region. | 12-30-2010 |
| 20110006437 | OPENING STRUCTURE - An opening structure includes a semiconductor substrate, at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall, a dielectric thin film covering at least a portion of the sidewall of each of the openings, and a metal layer filled in the openings. | 01-13-2011 |
| 20110143511 | Method of fabricating n-channel metal-oxide semiconductor transistor - A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer. | 06-16-2011 |
| 20120001338 | OPENING STRUCTURE - An opening structure is disclosed. The opening structure includes: a semiconductor substrate; at least one dielectric layer disposed on the semiconductor substrate, wherein the dielectric layer has a plurality of openings exposing the semiconductor substrate, and each of the openings has a sidewall; a dielectric thin film covering at least a portion of the sidewall of each of the openings; an etch stop layer disposed between the semiconductor substrate and the dielectric layer and extending partially into the openings to isolate the dielectric thin film from the semiconductor substrate; and a metal layer filled in the openings. | 01-05-2012 |
| 20120256273 | METHOD OF UNIFYING DEVICE PERFORMANCE WITHIN DIE - A method of unifying device performance within an integrated circuit die includes providing a layout of an integrated circuit die with multiple functional circuit blocks; filling a field between the multiple functional circuit blocks with dummy diffusion patterns; and filling the field between the multiple functional circuit blocks with dummy gate patterns such that the dummy gate patterns and the dummy diffusion patterns are completely overlapped. | 10-11-2012 |
Ming-Tsung Chen, Changhua County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110007452 | Lamellar Stacked Solid Electrolytic Capacitor - A lamellar stacked solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit is composed of a negative foil, an isolation paper with conductive polymer substance, a positive foil, an isolation paper with conductive polymer substance and a negative foil that are stacked onto each other in sequence, the positive foils of the capacitor units are electrically connected to each other, the negative foils of the capacitor units are electrically connected to each other, and the positive foils and the negative foils are insulated from each other. The substrate unit has a positive guiding substrate electrically connected to the positive foils of the capacitor units and a negative guiding substrate electrically connected to the negative foils of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit. | 01-13-2011 |
Ming-Tsung Chen, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080230917 | METHOD OF FABRICATING TWO-STEP SELF-ALIGNED CONTACT - A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper hole self-aligned to and communicated with the lower hole is formed in the second dielectric layer, wherein the upper hole and the lower hole constitute a self-aligned contact hole. Afterwards, the self-aligned contact hole is filled with a conductive layer. | 09-25-2008 |
| 20100308220 | INSPECTION STRUCTURE AND METHOD FOR IN-LINE MONITORING WAFER - The method for in-line monitoring a wafer is described as follows. A wafer is provided, and at least one inspection structure is then formed on the wafer in the following steps. An N-well region and a P-well region are formed in the wafer, wherein the N-well region and the P-well region are separated from each other. A gate on each of the N-well region and the P-well region is formed. A P-type doped region is respectively formed in the N-well region and in the P-well region at both sides of the gates. A first contact plug is formed on each P-type doped region, and second contact plug is formed on each gate. Afterwards, a defect inspection is conducted utilizing an electron beam inspection (EBI) system, such that a short between each first contact plug and each gate is determined. | 12-09-2010 |
Ming-Tsung Chen, Taoyuan Shien TW
| Patent application number | Description | Published |
|---|---|---|
| 20090157336 | STATIC MEASURING METHOD OF ELECTRICAL REFERENCES OF THREE-PHASE PERMANENT MAGNET SYNCHRONOUS MOTOR - A method for measuring a resistance and an inductance of a permanent magnet synchronous motor (PMSM) in a static state includes inputting a rated current of the PMSM and 150% of the rated current at a state of locking an axle of the PMSM, recording corresponding voltages V | 06-18-2009 |
Ming-Tsung Chen, Taichung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110186215 | APPARATUS AND METHOD FOR LAMINATING A FILM ON A WAFER - A method for laminating a film on a wafer includes a pre-cutting step: pre-cutting a dry film for fitting a size wafer size; a pre-attaching step: moving and pre-attaching the cut dry film on the wafer for corresponding the cut dry film and the wafer; a laminating step: laminating the cut dry film on the wafer with heating for fixing the cut dry film on the wafer. A flattening step: vertically and rigidly laminating the cut dry film on the wafer with heating again for flattening the cut dry film on the wafer. | 08-04-2011 |
| 20110186239 | FLATTENING MECHANISM FOR DRY FILM LAMINATOR - A flattening mechanism for dry film laminator includes a lower member connected to a dry film laminator. The lower member has a base portion formed thereon. The base portion has a plurality of air holes defined therein. The lower member has a lifting holder movably disposed thereon for holding a wafer. The wafer has a dry film disposed thereon. An upper member is movably disposed above the lower member. The upper member has a pressing portion disposed on a bottom thereof. The pressing portion has a steel plate disposed thereon and a first electric heating layer mounted on a top of the steel. A release film is movably guided between the upper member and the lower member, such that the wafer is lifted to press against the steel plate via the release film for enhancing a lamination of the dry film to the wafer and flattening the dry film. | 08-04-2011 |
| 20120103531 | APPARATUS FOR LAMINATING A FILM ON A WAFER - An apparatus for laminating a film on a wafer includes a cutting mechanism and a laminating mechanism. The cutting mechanism has a cutting device disposed thereon for pre-cutting a dry film. The cutting mechanism has a supporter disposed adjacent to the cutting device for positioning a wafer. The cutting mechanism has a suction member disposed and corresponding to the cutting device for sucking the cut dry film to allow the cutting device pre-cutting the dry film and moving the cut dry film to the supporter. The laminating mechanism has a first lower member provided for positioning the wafer and a first upper member disposed above the first lower member for laminating the cut dry film with electrically heating to adhere the cut dry film on the wafer. | 05-03-2012 |
Ming-Tsung Chen, Changhua County 506 TW
| Patent application number | Description | Published |
|---|---|---|
| 20120092810 | INSULATING ENCAPSULATION STRUCTURE FOR SOLID CHIP ELECTROLYTIC CAPACITOR - An insulating encapsulation structure is applied to a chip type solid electrolytic capacitor that includes an aluminum metallic body having an aluminum core layer. An upper oxide film and a lower oxide film respectively having fine holes on their surfaces are respectively formed on the top and the bottom of the aluminum core layer. On side surfaces of the metallic body is a plurality of cut burrs. The upper oxide film and the lower oxide film of the metallic body are respectively separated by a separating layer to form an anode and a cathode. The insulating encapsulation structure includes an insulating cover layer enclosing an outer surface of the metallic body to cover the cut burrs. Thereby, the required chemical conversion process is reduced along with current leakage, the overall manufacturing cost is lowered, and the mechanical strength for the edge of the metallic body is reinforced. | 04-19-2012 |
Ming-Tsung Chen, Tu-Cheng TW
| Patent application number | Description | Published |
|---|---|---|
| 20120198133 | ELECTRONIC DEVICE WITH EXPANDABLE MEMORY CAPACITY AND AN EXPANSION METHOD THEREOF - An electronic device includes a processor, an internal memory for storing system information and installing programs, and a memory expansion interface for connecting an expansion memory. The expansion memory is partitioned into at least one region to expand the internal memory. The internal memory is partitioned into a system region and a user region; the system region is used to store system information while the user region can be controlled and used by a user. The processor further includes a detection unit and a memory management unit. The detection unit detects the connection of the expansion memory to the memory expansion interface, and the memory management unit determines whether the expansion memory has been previously configured to expand the internal memory, and if not, the memory management unit associates the expansion memory with the internal memory to expand the internal memory. | 08-02-2012 |
| 20120264403 | COMMUNICATION CONTROL SYSTEM AND METHOD THEREOF - A communication control system includes an electronic device and a communication apparatus paired with the electronic device. The electronic device includes an input unit, a first BLUETOOTH unit, and a dialing control module. The input unit generates commands in response to operations of a user. The dialing control module generates dial information when a dialing command is received, and controls the first BLUETOOTH unit to transmit the dial information to the communication apparatus. The communication apparatus includes a wireless communication unit, a second BLUETOOTH unit, and a dialing module. The dialing module controls the wireless communication unit to dial according to the dial information. The dialing module also controls the second BLUETOOTH unit to transmit real-time dial information and voice signals of the user to the electronic device. A related method is also provided. | 10-18-2012 |
Ming-Tsung Chen, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120300369 | CONDUCTIVE STRUCTURE HAVING AN EMBEDDED ELECTRODE, AND SOLID CAPACITOR HAVING AN EMBEDDED ELECTRODE AND METHOD OF MAKING THE SAME - A solid capacitor having an embedded electrode includes a substrate unit, a first conductive unit, a second conductive unit, a first insulative unit, a third conductive unit, a second insulative unit, and an end electrode unit. The substrate unit includes a substrate body and a conductive body embedded into the substrate body. The substrate body has a lateral opening and a plurality of top openings, and the conductive body has a lateral conductive area exposed from the lateral opening and a plurality of top conductive areas respectively exposed from the top openings. The first conductive unit includes a plurality of first conductive layers respectively covering the top conductive areas. The second conductive unit includes a second conductive layer covering the first conductive layers. The porosity rate of the second conductive layer is larger than that of each first conductive layer. | 11-29-2012 |