Patent application number | Description | Published |
20090316366 | System and Method for Dissipating Heat From A Semiconductor Module - The system includes a circuit board, a semiconductor module, a heat dissipator, and at least one thermal via. The circuit board has substantially flat opposing first and second sides. The semiconductor module includes multiple semiconductor devices. The semiconductor module is oriented substantially parallel to the circuit board near the first side, while the heat dissipator is disposed near the second side. The thermal via extends through the circuit board to thermally couple the semiconductor module to the heat dissipator, which may be a heat spreader, heat sink, cooling fan, or heat pipe. | 12-24-2009 |
20100091537 | MULTI-DIE MEMORY DEVICE - An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission. | 04-15-2010 |
20100230807 | Method and Apparatus to Repair Defects in Nonvolatile Semiconductor Memory Devices - A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed. | 09-16-2010 |
20100315787 | System and Method for Dissipating Heat from Semiconductor Devices - A system includes a circuit board, a multi-die package, and a heat dissipator. The circuit board has substantially planar opposing first and second sides. The multi-die package includes a substrate and a first set of one or more semiconductor devices on a first substrate side and a second set of one or more semiconductor devices on a second substrate side. The multi-die package is located at the first circuit board side. The heat dissipator is located at the second circuit board side, and thermally coupled to the second set of semiconductor devices. One or more portions of the circuit board are removed between the first circuit board side and the second circuit board side so as to define one or more holes through the circuit board and to facilitate thermal coupling between the second set of semiconductor devices and the heat dissipator through the one or more holes. | 12-16-2010 |
20100320602 | High-Speed Memory Package - The semiconductor package includes a dielectric layer, a trace layer, a conductive layer, a die and an underfill layer. The dielectric layer has first side and an opposing dielectric layer second side. Multiple vias extend through the dielectric layer from the dielectric layer first side to the dielectric layer second side. Multiple solder balls are disposed at the dielectric layer second side. Each of the solder balls is electrically coupled to a different one of the vias. The die is electrically coupled to the solder balls. The conductive layer is disposed between the dielectric layer second side and the die. The conductive layer defines a window there through for allowing the solder balls to electrically couple to the vias without contacting the conductive layer, i.e., no physical or electrical contact. The underfill layer is formed between the die and the conductive layer, while the trace layer is formed at the dielectric layer first side. Traces of the trace layer electrically couple the vias to other solder balls. | 12-23-2010 |
20110119425 | DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM - The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module. | 05-19-2011 |
20120182776 | DRAM DEVICE WITH BUILT-IN SELF-TEST CIRCUITRY - A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells. | 07-19-2012 |
20120187578 | PACKAGED SEMICONDUCTOR DEVICE FOR HIGH PERFORMANCE MEMORY AND LOGIC - A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias. | 07-26-2012 |
20120236668 | MEMORY MODULE WITH DISCRETE HEATING ELEMENT - A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects. | 09-20-2012 |
20120294058 | MULTI-DIE MEMORY DEVICE - A multi-die memory device includes a first die of a first type and configured to electrically interface with an external processor via a first synchronous interface operating at a first clock rate, and at least one second die of a second type and configured for data storage. Each second die transacts data with the first die via a second synchronous interface operating at a second clock rate, where the first clock rate is an integer multiple of the second clock rate, and where a timing reference associated with the second synchronous interface is transmitted by the first die to the second die. | 11-22-2012 |
20140247637 | MULTI-DIE MEMORY DEVICE - A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays. | 09-04-2014 |
20150066824 | METHODS AND SYSTEMS FOR GENOMIC ANALYSIS - A computer-implemented method for processing and/or analyzing nucleic acid sequencing data comprises receiving a first data input and a second data input. The first data input comprises untargeted sequencing data generated from a first nucleic acid sample obtained from a subject. The second data input comprises target-specific sequencing data generated from a second nucleic acid sample obtained from the subject. Next, with the aid of a computer processor, the first data input and the second data input are combined to produce a combined data set. Next, an output derived from the combined data set is generated. The output is indicative of the presence or absence of one or more polymorphisms of the first nucleic acid sample and/or the second nucleic acid sample. | 03-05-2015 |