Patent application number | Description | Published |
20130292830 | Interposer Having a Defined Through Via Pattern - A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone. | 11-07-2013 |
20140138816 | Method for Forming Package-on-Package Structure - A method comprises attaching a semiconductor die on a first side of a wafer, attaching a first top package on the first side of the wafer and attaching a second top package on the first side of the wafer. The method further comprises depositing an encapsulation layer over the first side of the wafer, wherein the first top package and the second top package are embedded in the encapsulation layer, applying a thinning process to a second side of the wafer, sawing the wafer into a plurality of chip packages and attaching the chip package to a substrate. | 05-22-2014 |
20140162405 | Interposer Having a Defined Through Via Pattern - A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone. | 06-12-2014 |
20140167263 | Methods and Apparatus for Package with Interposers - Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well. | 06-19-2014 |
20140252657 | Package Alignment Structure and Method of Forming Same - An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line. | 09-11-2014 |
20150035161 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A singulated semiconductor structure comprises a molding compound; a first conductive post in the molding compound having a first geometric shape in a top view; a second conductive post or an alignment mark in the molding compound having a second geometric shape in a top view, wherein the second geometric shape is different from the first geometric shape. The second conductive post or an alignment mark can be positioned at the corner, the center, the edge, or the periphery of the singulated semiconductor structure. The second geometric shape can be any geometric construct distinguishable from the first geometric shape. The second conductive post or an alignment mark can be placed at an active area or a non-active area of the singulated semiconductor structure. | 02-05-2015 |
20150061116 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad. | 03-05-2015 |
20150069606 | Methods and Apparatus for Package on Package Devices - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package. | 03-12-2015 |
20150108635 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device. | 04-23-2015 |
20150118797 | Method for Singulating Packaged Integrated Circuits and Resulting Structures - A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through a top portion of the molding compound using a first beveled saw blade, while leaving a bottom portion of the molding compound remaining. The method further includes sawing through the bottom portion of the molding compound and the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the first saw blade. The resulting structure is within the scope of the present disclosure. | 04-30-2015 |
20150125997 | Method for Singulating Packaged Integrated Circuits and Resulting Structures - A method of packaging an integrated circuit includes forming a first integrated circuit and a second integrated circuit on a wafer, the first and second integrated circuit separated by a singulation region. The method includes covering the first and second integrated circuits with a molding compound, and sawing through the molding compound and a top portion of the wafer using a beveled saw blade, while leaving a bottom portion of the wafer remaining. The method further includes sawing through the bottom portion of the wafer using a second saw blade, the second saw blade having a thickness that is less than a thickness of the beveled saw blade. The resulting structure is within the scope of the present disclosure. | 05-07-2015 |
20150130020 | SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. | 05-14-2015 |
20150179561 | Methods and Apparatus for Package with Interposers - Methods and apparatus for an interposer with dams used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A plurality of dams may be formed above the metal layer around each corner of the metal layer. Dams may be formed on both sides of the interposer substrate. A dam surrounds an area where connectors such as solder balls may be located to connect to other packages. A non-conductive dam may be formed above the dam. An underfill may be formed under the package connected to the connector, above the metal layer, and contained within the area surrounded by the dams at the corner, so that the connectors are well protected by the underfill. Such dams may be further formed on a printed circuit board as well. | 06-25-2015 |
20150200173 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a conductive bump for disposing over a substrate and an elongated ferromagnetic member surrounded by the conductive bump, including a first end and a second end, and extending from the first end to the second end, the elongated ferromagnetic member is disposed substantially orthogonal to the substrate to dispose the conductive bump at a predetermined orientation and at a predetermined position of the substrate. Further, a method of manufacturing a semiconductor structure includes providing a substrate, forming a conductive trace within the substrate, applying an electric current passing through the conductive trace to generate an electromagnetic field and disposing a conductive bump including an elongated ferromagnetic member in a predetermined orientation and at a predetermined position above the substrate in response to the electromagnetic field generated by the conductive trace. | 07-16-2015 |