Patent application number | Description | Published |
20090101966 | Method of identifying logical information in a programming and erasing cell by on-side reading scheme - A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme. | 04-23-2009 |
20100265773 | 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE - A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory. | 10-21-2010 |
20100290293 | METHOD OF IDENTIFYING LOGICAL INFORMATION IN A PROGRAMMING AND ERASING CELL BY ON-SIDE READING SCHEME - A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme. | 11-18-2010 |
20110317480 | PHASE CHANGE MEMORY CODING - An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit. | 12-29-2011 |
20120170359 | Phase Change Memory With Fast Write Characteristics - A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells. | 07-05-2012 |
20120188813 | VERIFICATION ALGORITHM FOR METAL-OXIDE RESISTIVE MEMORY - Memory devices and methods for operating such devices are described which can effectively program the metal-oxide memory elements in an array, while also avoiding applying unnecessarily high voltage pulses. Programming operations described herein include applying a lower voltage pulse across a metal-oxide memory element to establish a desired resistance state, and only applying a higher voltage pulse when the lower voltage pulse is insufficient to program the memory element. In doing so, issues associated with applying unnecessarily high voltages across the memory element can be avoided. | 07-26-2012 |
20120320669 | MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode. | 12-20-2012 |
20140027706 | SWITCHING DEVICE AND OPERATING METHOD FOR THE SAME AND MEMORY ARRAY - A switching device and an operating method for the same and a memory array are provided. The switching device comprises a first solid electrolyte, a second solid electrolyte and a switching layer. The switching layer is adjoined between the first solid electrolyte and the second solid electrolyte. | 01-30-2014 |
20140203235 | CONDUCTIVE BRIDGE RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer. | 07-24-2014 |
20140203237 | SELF-RECTIFIED DEVICE, METHOD FOR MANUFACTURING THE SAME, AND APPLICATIONS OF THE SAME - A self-rectified device is provided, comprising a bottom electrode, a patterned dielectric layer with a contact hole formed on the bottom electrode, a memory formed at the bottom electrode and substantially aligned with the contact hole, and a top electrode formed on the bottom electrode and filling into the contact hole to contact with the memory, wherein the top electrode comprises a N+ type semiconductor material or a P+ type semiconductor material, and the memory and the top electrode produce a self-rectified property. | 07-24-2014 |
20140376308 | PHASE CHANGE MEMORY, WRITING METHOD THEREOF AND READING METHOD THEREOF - A phase change memory (PCM), a writing method thereof and a reading method thereof are provided. The PCM has a plurality of memory cells. The writing method comprises the following steps. At least one stress pulse is applied for aging at least one of the memory cells. A starting pulse is applied to all of the memory cells of the PCM for decreasing a resistance of each memory cell. A detection pulse is applied to all of the memory cells of the PCM for detecting the resistance of each memory cell. A set pulse is applied to the aged memory cells. A reset pulse is applied to the non-aged memory cells. | 12-25-2014 |
20150138871 | MEMORY STRUCTURE AND OPERATION METHOD THEREFOR - Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element changes from a first resistance state into a second resistance state; and in an erase operation, generating an erase current from a well region of the transistor to the resistive memory element but keeping the erase current from flowing through the transistor, so that the resistance state of the resistive memory element changes from the second resistance state into the first resistance state. | 05-21-2015 |
Patent application number | Description | Published |
20090040728 | Fixing Structure and Heat Dissipation Device - A fixing structure includes a back plate, a fixing plate, a first elastic element, a second elastic element and a fastener. The back plate has a positioning pillar thereon. The fixing plate presses a heat dissipation element to allow the heat dissipation element to contact a chip above the back plate. Both the first elastic element and the second elastic element are connected to the fixing plate. The fastener fastens the first elastic element and the second elastic element to the positioning pillar or just fastens the first elastic element to the positioning pillar to allow the second elastic element to be suspended. Furthermore, a heat dissipation device employing the fastening structure is also disclosed. | 02-12-2009 |
20140311713 | HEAT DISSIPATION COMPONENT - A heat dissipation component includes a first film, a second film, and a working fluid. The second film is connected with a part of the first film to form a plurality of vein channels. The vein channels include a main vein channel and a plurality of branch vein channels, and the main vein channel is connected with the branch vein channels. The working fluid is disposed in the vein channels. The heat dissipation component is bendable to be easily assembled with an electronic device. The working fluid may flow in the vein channels via a pressure difference generated by a phase transition, gravity, and a capillary effect, or via a pressure difference generated, by a pulse generator to transfer the heat to the whole heat dissipation component. The first film and the second film may have heat conduction material to improve the heat transfer rate. | 10-23-2014 |
20150030441 | FAN BLADE STRUCTURE AND CENTRIFUGAL FAN USING THE SAME - A fan blade structure applied to a centrifugal fan is provided. The fan blade structure includes a wheel hub and an annular vane. The wheel hub includes a plurality of connecting brackets, and the annular vane includes multiple crests and troughs which interlace to form a continuous curved surface. The continuous curved surface has an outer ring surface and an inner ring surface. The connecting brackets are connected to the inner ring surface and drive the annular vane to rotate. | 01-29-2015 |