Patent application number | Description | Published |
20080206919 | METHOD OF MANUFACTURE OF A MICROLENS STRUCTURE FOR OPTO-ELECTRIC SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor material substrate, an opto-electric component formed on the substrate, and a first transparent layer formed on an upper surface of the substrate over the component, the layer having a planar upper surface with a cavity formed therein. The first transparent layer has a selected thickness and a first index of refraction. The semiconductor device further includes a lens having a second index of refraction, the lens being formed in the cavity by flowing a flowable dielectric over the substrate. An upper surface of the lens and the upper surface of the transparent layer may be coplanar, or alternatively, they may lie in separate planes. The semiconductor device may also include a second transparent layer formed over the first layer and lens, as a passivation layer. | 08-28-2008 |
20090169190 | Heating system and method for microfluidic and micromechanical applications - An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof. | 07-02-2009 |
20100163116 | MICROFLUIDIC NOZZLE FORMATION AND PROCESS FLOW - A method that includes forming a chamber in a substrate, forming a silicon layer overlying the chamber, etching the silicon layer to remove selected regions and retain a selected portion overlying the chamber, the selected portion being at a location and having dimensions that correspond to a location and to dimensions of a nozzle, and forming a first metal layer adjacent to the selected portion. The method also includes forming a path in the substrate to expose the chamber concurrently with removing the selected portion of the silicon layer to expose the nozzle, the nozzle being in fluid communication with the path, the chamber, and a surrounding environment. | 07-01-2010 |
20100163517 | METHOD TO FORM A RECESS FOR A MICROFLUIDIC DEVICE - A method includes forming a recess in a first surface of a substrate, the recess having a width, depth, and height selected to correspond to a width, depth, and height of a fluid chamber, forming a sacrificial material in the recess, forming a first heater element, forming a metal layer overlying the first heater element, and forming a nozzle opening in the metal layer to expose the sacrificial material. The method also includes forming a path from a second surface of the substrate to expose the sacrificial material and removing the sacrificial material from the recess to expose the chamber with the selected width, depth, and height, the chamber in fluid communication with the path, the nozzle opening, and a surrounding environment. | 07-01-2010 |
20100167497 | USE OF FIELD OXIDATION TO SIMPLIFY CHAMBER FABRICATION IN MICROFLUIDIC DEVICES - A method includes growing a first oxide region concurrently with a second oxide region in a substrate and forming an inlet path to the first oxide region, the inlet path exposing a first surface of the first oxide region. The method also includes removing the first oxide region to form a chamber, forming a first MOS transistor adjacent the second oxide region, and forming a second MOS transistor separated from the first MOS transistor by the second oxide region. | 07-01-2010 |
20110081138 | HEATING SYSTEM AND METHOD FOR MICROFLUIDIC AND MICROMECHANICAL APPLICATIONS - An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof. | 04-07-2011 |
20120161573 | SURFACE ALLOY PROCESS FOR MEMS AND NEMS - A method of manufacturing microstructures, such as MEMS or NEMS devices, including forming a protective layer on a surface of a moveable component of the microstructure. For example, a silicide layer may be formed on one or more surfaces of a poly-silicon mass that is moveable with respect to a substrate of the microstructure. The process may be self-aligning. | 06-28-2012 |
20120168896 | DOUBLE SIDE WAFER PROCESS, METHOD AND DEVICE - A method of manufacturing double-sided semiconductor die by performing a first plurality of processes to a first side of a wafer and performing a second plurality of processes to a second side of the wafer, thereby forming at least a first semiconductor device on the first side of the wafer and at least a second semiconductor device on the second side of the wafer. The wafer may be cut to form a plurality of die having at least one semiconductor device on each side. | 07-05-2012 |
20140304990 | HEATING SYSTEM AND METHOD FOR MICROFLUIDIC AND MICROMECHANICAL APPLICATIONS - An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof. | 10-16-2014 |
20150070045 | ULTRA FAST TRANSISTOR THRESHOLD VOLTAGE EXTRACTION - A method for performing a semiconductor parametric test comprising performing a full voltage sweep for a first component on a first semiconductor wafer to determine a first value of an electrical characterization parameter for the first component, wherein the full voltage sweep comprises a range between about a minimum input voltage level of the first component and about a maximum input voltage level of the first component, determining a smart sensing window (SSW) for a plurality of subsequent components on the first semiconductor wafer according to the first value, wherein the SSW comprises a range comprising a portion of the full voltage sweep range, performing a partial voltage sweep in the SSW for each of the subsequent components to determine a second value of the electrical characterization parameter for each of the subsequent semiconductor components, and adapting the SSW for at least some of the subsequent components. | 03-12-2015 |