| Patent application number | Description | Published |
|---|
| 20090317214 | NOVEL WAFER'S AMBIANCE CONTROL - A semiconductor manufacturing system, an interface system, a carrier, and a method for providing an ambient controlled environment is disclosed. The semiconductor manufacturing system comprises a plurality of process chambers; at least one interface system, wherein the interface system includes a first ambient control element; at least one carrier, wherein the carrier comprises a second ambient control element; and a control module coupled to the plurality of process chambers, the at least one interface system, and the at least one carrier. | 12-24-2009 |
| 20100015894 | CMP by Controlling Polish Temperature - A method for manufacturing integrated circuits on a wafer includes providing a facility-supplied room temperature solution; controlling the temperature of the facility-supplied room temperature solution to a desired temperature set point to generate a rinse solution; and rinsing a polishing pad using the rinse solution. The wafer is then polished by means of a chemical mechanical polishing process. | 01-21-2010 |
| 20100018029 | Rinsing Wafers Using Composition-Tunable Rinse Water in Chemical Mechanical Polish - An apparatus for manufacturing integrated circuits on a wafer includes a polish pad; a rinse arm movable over the polish pad; and a post-polish cleaner. The post-polish cleaner includes a brush for brushing the wafer; and a nozzle aiming at the wafer. The apparatus further includes a mixer configured to mix an additive and di-ionized water; and a pipe connecting the mixer to at least one of the rinse arm and the nozzle. | 01-28-2010 |
| 20110062580 | PROTECTION LAYER FOR PREVENTING UBM LAYER FROM CHEMICAL ATTACK AND OXIDATION - A protection layer formed of a CuGe | 03-17-2011 |
| 20110092064 | Preventing UBM Oxidation in Bump Formation Processes - A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction/purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer. | 04-21-2011 |
| 20110101527 | MECHANISMS FOR FORMING COPPER PILLAR BUMPS - The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The conductive layer can be a metal pad, a post passivation interconnect (PPI) layer, or a top metal layer. By performing an in-situ deposition of a protective conductive layer over the conductive layer (or base conductive layer), the under bump metallurgy (UBM) layer of the metal bump adheres better to the conductive layer and reduces the occurrence of interfacial delamination. In some embodiments, a copper diffusion barrier sub-layer in the UBM layer can be removed. In some other embodiments, the UBM layer is not needed if the metal bump is deposited by a non-plating process and the metal bump is not made of copper. | 05-05-2011 |
