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| 20090129353 | METHOD FOR RECOGNIZING AVAILABLE CHANNEL IN IEEE 802.15.4 PROTOCOL CSMA/CA MECHANISM - Disclosed is a method of recognizing an available channel in order to prevent channel occupation requirements from colliding with each other when one wireless channel is shared by plural terminals in a CSMA/CA mechanism using an IEEE 802.15.4 protocol slot, the method including: a first step of initializing a counter, CW, as 2, the CW being used for CCA which an attempt to perform is made before frame transmission; a second step of determining if a required channel is occupied; a third step of decreasing the CW by 1 when the channel is idle in the second step; a fourth step of re-determining if the channel is occupied; and a fifth step of, based on a determination result in the fourth step, determining if the CW is 1 when the channel is occupied. | 05-21-2009 |
| 20090154489 | METHOD FOR DISTRIBUTING CONTENTION AMONG TERMINALS IN CONTENTION ACCESS PERIOD OF SUPERFRAME - Disclosed is a method for distributing contention among terminals in a Contention Access Period (CAP) of a superframe in regard to a Medium (or Media) Access Control (MAC) layer employing a beacon-enabled mode in IEEE 802.15.4 standard. The method includes: dividing the CAP or the superframe into a plurality of sub-periods, all having the same size; receiving an association request message from a relevant terminal; and allocating one of the plurality of sub-periods to the relevant terminal, and transferring information on the sub-periods to the relevant terminal through a beacon frame, by a Personal Area Network (PAN) coordinator. | 06-18-2009 |
| 20090175622 | METHOD FOR ALLOCATING UPSTREAM TRANSMISSION BANDWIDTH IN WDM-EPON - Disclosed is a method fox allocating upstream transmission bandwidth so as to prevent Inter-Scheduling Cycle Gaps (ISCGs) from occurring in an N number of Optical Network Units (ONUs) by using an m number of wavelength channels for upstream transmission in a Wavelength-Division Multiplexing (WDM)-Ethernet Passive Optical Network (EPON). The method includes: grouping the ONUs to be allocated each of the m number of wavelength channels; and performing a Dynamic Bandwidth Allocation (DBA) algorithm in order for the grouped ONUs to efficiently use allocated wavelengths and time slots, thereby allocating each wavelength channel. Accordingly, by using a scheme of managing ONUs by each group, it is possible to more efficiently allocate bandwidth than the online scheduling scheme. As compared with the offline scheduling scheme, ISCGs caused by bandwidth allocation do not occur. | 07-09-2009 |
| 20090190606 | SYSTEM AND METHOD FOR POLLING IN ETHERNET PASSIVE OPTICAL NETWORK - Disclosed is a system and a method for polling in an Ether net Passive Optical Network (EPON). The system includes: multiple Optical Network Units (ONUs) for sharing optical channels of the EPON with one another and transmitting traffic; and an Optical Line Terminal (OLT) for discriminating a plurality of ONUs gaining access to the EPON among the multiple ONUs and then collecting routing information on the plurality of ONUs gaining access to the EPON, and for classifying the plurality of ONUs gaining access to the EPON into two or more ONU groups according to the collected routing information and then carrying out forming a polling cycle and allocating bandwidth on each ONU group. Therefore, a transmission idle period in a traffic channel is not only minimized, but an availability ratio of traffic channels can also be maximized. | 07-30-2009 |
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| 20090282188 | MEMORY DEVICE AND CONTROL METHOD - A memory device includes a first controller and a second controller. The first controller receives a first command from a host and stores the first command in a first command queue, and transmits the first command to the second controller relating to the first command stored in the first command queue. The second controller transmits the first command stored in the second command queue to a flash memory. | 11-12-2009 |
| 20100088467 | MEMORY DEVICE AND OPERATING METHOD OF MEMORY DEVICE - A memory device may include a non-volatile memory and non-volatile RAM. The non-volatile memory may include a data block and a metadata block. Metadata information with respect to the data block may be included in the metadata block. A portion of metadata with respect to the data block or the metadata with respect to the metadata block may be stored in the non-volatile RAM. | 04-08-2010 |
| 20100131736 | MEMORY DEVICE AND METHOD OF OPERATION - A memory device includes a data block storing first data, and a log block storing second data that is an updated value of the first data. A spare area of the log block stores a first mapping table including mapping information between the first data and the second data. | 05-27-2010 |
| 20100146163 | MEMORY DEVICE AND MANAGEMENT METHOD OF MEMORY DEVICE - A memory device and a method of managing a memory are provided. The memory device includes a command queue configured to receive a first command from a host to store the first command, and to read and transmit the first command, a controller configured to read, from a storage device, data corresponding to the first command transmitted from the command queue, and to store the data in a buffer memory, and a first memory configured to store a data list of data stored in the buffer memory, wherein, in response to the command queue receiving the first command from the host, the controller updates the data list of data stored in the first memory. | 06-10-2010 |
| 20100235566 | FLASH MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - Described herein is a flash memory apparatus and method controlling the same. The flash memory apparatus includes a processor and one or more flash memory units. The processor controls one or more memory operations performed in the one or more flash memory units. The processor stops controlling a memory operation in a flash memory unit when the memory operation is performed, and continues performing the memory operation in the flash memory unit when the flash memory unit generates an interrupt signal. | 09-16-2010 |
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| 20090027529 | Image sensor with wide operating range - An image sensor includes a photoelectric converter, a source-follower transistor, and a selection transistor. The photoelectric converter generates electric charge in response to received light, and the electric charge varies a voltage of a detection node. The source-follower transistor is coupled between the detection node and an output node and has a first threshold voltage. The selection transistor is coupled between the source-follower transistor and a voltage node with a power supply voltage or a boosted voltage applied thereon, and has a second threshold voltage with a magnitude that is less than a magnitude of the first threshold voltage such that the source-follower transistor operates in saturation. | 01-29-2009 |
| 20090130792 | Method of fabricating image sensor - A method of fabricating an image sensor includes forming a photoelectric transformation device on a substrate and forming a dielectric layer structure on the substrate. The dielectric layer structure includes multi-layer interlayer dielectric layers and multi-layer metal interconnections which are located between the multi-layer interlayer dielectric layers. A cavity which penetrates the multi-layer interlayer dielectric layers on the photoelectric transformation device is formed. A heat treatment is performed on the substrate on which the cavity is formed. | 05-21-2009 |
| 20090137111 | METHOD OF FABRICATING METAL INTERCONNECTION AND METHOD OF FABRICATING IMAGE SENSOR USING THE SAME - A method of fabricating a metal interconnection and a method of fabricating image sensor using the same are provided. The method of fabricating a metal interconnection including forming a interlayer dielectric layer on a substrate, forming an interconnection formation region in the interlayer dielectric layer, performing an ultraviolet (UV) treatment on the substrate after the interconnection formation region is formed and forming a metal interconnection in the interconnection formation region. | 05-28-2009 |
| 20110294288 | METHOD OF FABRICATING METAL INTERCONNECTION AND METHOD OF FABRICATING IMAGE SENSOR USING THE SAME - A method of fabricating a metal interconnection and a method of fabricating image sensor using the same are provided. The method of fabricating a metal interconnection including forming a interlayer dielectric layer on a substrate, forming an interconnection formation region in the interlayer dielectric layer, performing an ultraviolet (UV) treatment on the substrate after the interconnection formation region is formed and forming a metal interconnection in the interconnection formation region. | 12-01-2011 |
| 20120009719 | IMAGE SENSORS INCLUDING HYDROPHOBIC INTERFACES AND METHODS OF FABRICATING THE SAME - A method of fabricating an image sensor device includes forming an insulating layer on a substrate including a photodiode therein, and forming a wiring structure on the insulating layer. The wiring structure includes at least one wiring layer and at least one insulating interlayer. A cavity is formed extending into the wiring structure over the photodiode to expose a surface of the at least one insulating interlayer. The surface of the at least one insulating interlayer exposed by the cavity is modified to define a hydrophobic surface. Related systems and devices are also discussed. | 01-12-2012 |
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| 20100029892 | FLUORENE-BASED RESIN POLYMER AND METHOD FOR PREPARING THEREOF - The present invention relates to a fluorene-based resin polymer having a repeating unit of Formula 1 and a method for preparing the same. The fluorene-based resin polymer has a high molecular weight and low acid value, and has an excellent developing property, adhesive property, and stability. | 02-04-2010 |
| 20100105793 | Polymer Resin Compounds And Photoresist Composition Including New Polymer Resin Compounds - The present invention relates to a polymer resin compound including a new polycyclic compound, and a photosensitive resin composition including the polymer resin compound as an effective binder matrix. In particular, the photosensitive resin composition according to the present invention uses a polymer resin compound, which includes a compound having double cyclic structure in one molecule as a monomer, as a binder matrix. Accordingly, the photosensitive resin composition has an excellent photosensitivity and an excellent developing property, and has a low distortion property during plastic processing. For this reason, the photosensitive resin composition has an advantage of curing various transparent photosensitive materials used to manufacture a color filter of a liquid crystal display, for example, a column spacer, an overcoat, a passivation material, and the like. | 04-29-2010 |
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| 20080278921 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME, AND PRINTED CIRCUIT BOARD - Provided are a semiconductor package, a method of forming the semiconductor package, and a printed circuit board (PCB). The semiconductor package includes: a PCB including at least two parts divided by an isolation region; a semiconductor chip mounted on the PCB; and a molding layer disposed in the isolation region. The method includes: preparing a PCB, the PCB including a plurality of chip regions and a scribe region; forming isolation regions dividing each of the chip regions into two parts, the isolation regions including inner isolation regions and outer isolation regions, the inner isolation regions being provided in the chip regions, the outer isolation regions being provided at both ends of the inner isolation regions so as to extend toward the scribe region; mounting semiconductor chips on the chip regions; and cutting the PCB along the scribe region to divide the chip regions into at least two parts. | 11-13-2008 |
| 20080291652 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME, PRINTED CIRCUIT BOARD, AND ELECTRONIC DEVICE - Provided are a semiconductor package and a method for forming the same, and a PCB (printed circuit board). The semiconductor package comprises: a PCB including a slit at a substantially central portion thereof, the PCB including an upper surface and a lower surface; a semiconductor chip mounted on the upper surface of the PCB; an upper molding layer disposed on the upper surface and covering the semiconductor chip; and a lower molding layer filling the slit and covering a portion of the lower surface of the PCB, wherein the PCB comprises a connecting recess at a side surface thereof, and the upper molding layer and the lower molding layer are in contact with each other at the connecting recess. | 11-27-2008 |
| 20080308913 | STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A stacked semiconductor package includes a first semiconductor package, a second semiconductor package and a conductive connection member. The first semiconductor package includes a first semiconductor chip, a first lead frame having first outer leads that are electrically connected to the first semiconductor chip, and a first molding member formed on the first semiconductor chip and the first lead frame to expose the first outer leads. The second semiconductor package includes a second semiconductor chip, a second lead frame formed on the first molding member and having second outer leads that may be electrically connected to the second semiconductor chip, and a second molding member formed on the second semiconductor chip and the second lead frame to expose the second outer leads. The conductive connection member may electrically connect the first outer leads and the second outer leads to each other. Further, the conductive connection member may have a crack-blocking groove. | 12-18-2008 |
| 20090184410 | SEMICONDUCTOR PACKAGE APPARATUS HAVING REDISTRIBUTION LAYER - Provided is a semiconductor package apparatus having a redistribution layer. The apparatus includes at least one or more semiconductor chips, a packing part protecting the semiconductor chips, and a support part supporting the semiconductor chips. The apparatus also includes external terminals extending outside the packing part, redistribution layers installed between the semiconductor chips and the support part and including redistribution paths, first signal transmitting units, and second signal transmitting units. The first signal transmitting units transmitting electrical signals generated from the semiconductor chips to the redistribution paths of the redistribution layers, and the second signal transmitting units transmit the electrical signals from the redistribution paths to the external terminals. Therefore, a size and a thickness of the semiconductor package apparatus can be reduced, and processes can be simplified to improve productivity. | 07-23-2009 |
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| 20080237889 | Semiconductor package, method of fabricating the same, and semiconductor package mold - Provided is a semiconductor package, which may include a plurality of semiconductor chips to form a multi-stack semiconductor package (MSP), a method of fabricating the semiconductor package and the MSP, and a semiconductor package mold for fabricating the semiconductor package. The semiconductor package may include a first semiconductor chip package having a first substrate including a first surface having a center portion on which a first semiconductor chip is mounted, and at least one first boundary portion on which a plurality of conductive connection pad groups are formed, and a molding member including a body that covers the first semiconductor chip, and at least one extension that extends from the body towards a corner portion of the first surface of the first substrate, wherein the extension extends while avoiding the conductive connection pad group. The semiconductor package may further include a second semiconductor chip package stacked on the first semiconductor chip package, the second semiconductor chip including a second substrate on which at least one second semiconductor chip that is electrically connected to the conductive connection pad group may be mounted. | 10-02-2008 |
| 20090121332 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package includes a lead frame, an insulation member, a chip, bonding wires and a sealing member. The lead frame includes a plurality of first leads and a plurality of second leads. The second leads have a chip adhesion region. The insulation member fills a space between the second leads in the chip adhesion region. The chip is provided on at least one surface of the insulation member. The chip has single-side bonding pads. The bonding wires electrically connect the leads and the bonding pads. The sealing member covers the lead frame, the insulation member, the chip and the bonding wires. Since the space between the second leads is filled with the insulation member, voids may be prevented from occurring. | 05-14-2009 |
| 20100007007 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a semiconductor chip having a first surface, and a second surface that is opposite to the first surface and allows a semiconductor device to be formed thereon; bonding pads disposed on the second surface of the semiconductor chip; and a metal ion barrier layer disposed on the first surface of the semiconductor chip, and preventing metal ions from penetrating into the semiconductor chip through the first surface of the semiconductor chip. Accordingly, the semiconductor package can obtain a superior semiconductor device by minimizing moisture absorption and effectively blocking the penetration of metal ions. | 01-14-2010 |
