| Patent application number | Description | Published |
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| 20090170265 | Method of Fabricating a Recess Gate Type Transistor - A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween. | 07-02-2009 |
| 20090173996 | Recess Gate Type Transistor - A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween. | 07-09-2009 |
| 20090256209 | Gate Structure of Semiconductor Device - A gate structure of a semiconductor device comprising a silicon substrate having a field oxide film, a plurality of gates formed by sequentially stacking a first gate dielectric film, a first gate conductive film, and a gate silicide film on the silicon substrate. a thermal oxide film formed on a side of the first gate conductive film, a plurality of trenches formed between the gates, a second gate oxide film formed on an interior wall of each trench; and a second conductive film formed in a spacer shape on a predetermined region of the second gate oxide film, and on a side of the first gate conductive film, the gate silicide film and the thermal oxide film. | 10-15-2009 |
| 20100041196 | Method for Fabricating a Transistor having a Recess Gate Structure - A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate. | 02-18-2010 |
| 20100099244 | PARTIAL IMPLANTATION METHOD FOR SEMICONDUCTOR MANUFACTURING - Disclosed herein is a partial implantation method for manufacturing semiconductor devices. The method involves implantation of dopant ions at different densities into a plurality of wafer regions, including first and second regions, defined in a wafer by means of a boundary line. In the method, first, second and third implantation zones are defined. The first implantation zone is the remaining part of the first region except for a specific part of the first region close to the boundary line, the second implantation zone is the remaining part of the second region except for a specific part of the second region close to the boundary line, and the third implantation zone is the remaining part of the wafer except for the first and second implantation zones. Then, dopant ions are implanted into the first implantation zone at a first density, into the second implantation zone at a second density different from the first density, and into the third implantation zone at a third density that is a midway value between the first and second densities. | 04-22-2010 |
| 20100294655 | RADIOISOTOPE PRODUCTION O-18 WATER TARGET HAVING IMPROVED COOLING PERFORMANCE - A target apparatus for producing a radioisotope having improved cooling performance including a cavity member including a cavity accommodating H | 11-25-2010 |
| Patent application number | Description | Published |
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| 20090039334 | PHASE-CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase-change memory device and a fabrication method thereof, capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode. The method of fabricating the phase-change memory device includes the steps of preparing a semiconductor substrate having a junction area formed with a dielectric layer, forming an interlayer dielectric layer having etching selectivity lower than that of the dielectric layer over an entire structure, and forming a contact hole by removing predetermined portions of the interlayer dielectric layer and the dielectric layer. The contact area between the PN diode and the semiconductor substrate is increased so that interfacial resistance is reduced. | 02-12-2009 |
| 20090045389 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes. | 02-19-2009 |
| 20090321705 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate, a first conductive pattern formed on the semiconductor substrate, a second conductive pattern contacting an upper surface of the first conductive pattern and having a diameter less than a diameter of the first conductive pattern, and a phase change material layer contacting the second conductive pattern. | 12-31-2009 |
