Patent application number | Description | Published |
20080219048 | Multibit electro-mechanical memory device and method of manufacturing the same - A multibit electro-mechanical memory device capable of increasing an integrated level of memory devices, and a method of manufacturing the same, are provided. The memory device includes a substrate, a bit line on the substrate; a lower word line and a trap site isolated from the bit line, a pad electrode isolated from a sidewall of the trap site and the lower word line and connected to the bit line, a cantilever electrode suspended over a lower void in an upper part of the trap site, and connected to the pad electrode and curved in a third direction vertical to the first and second direction by an electrical field induced by a charge applied to the lower word line, a contact part for concentrating a charge induced from the cantilever electrode thereon in response to the charge applied from the lower word line and the trap site, the contact part protruding from an end part of the cantilever electrode, and an upper word line formed with an upper void on the cantilever electrode. | 09-11-2008 |
20090057761 | Fin field effect transistor and method of manufacturing the same - Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current. | 03-05-2009 |
20090072296 | Multibit electro-mechanical device and method of manufacturing the same - A multibit electro-mechanical memory device capable of increasing an integrated level of memory devices, and a method of manufacturing the same, are provided. The memory device includes a substrate, a bit line in a first direction on the substrate, a lower word line insulated from the bit line and in a second direction intersecting the first direction, a pad electrode isolated from a sidewall of the lower word line and connected to the bit line, a cantilever electrode expending in the first direction over the lower word line with a lower void therebetween, and connected to the pad electrode and curved in a third direction vertical to the first and second direction by an electrical field induced by a charge applied to the lower word line, a trap site expending in the second direction over the cantilever electrode with an upper void therebetween, and an upper word line to which a charge to curve the cantilever electrode in a direction of the trap site is applied, the upper word line on the trap site. | 03-19-2009 |
20090072297 | Multibit electro-mechanical memory device and method of manufacturing the same - A memory device comprises a cantilever electrode comprising a first portion that is supported by a pad electrode, and that extends from the pad electrode, and further comprising a second portion that arches over an upper part of the lower word line, wherein a lower void is between the second portion of the cantilever electrode and the lower word line, and wherein the second portion of the cantilever electrode, in a first position, is curved, wherein a trap site extends above the cantilever electrode, the trap site separated from the cantilever electrode by an upper void, and wherein an upper word line on the trap site receives a charge that enables the second portion of the cantilever electrode, in a second position, to be curved toward the trap site. | 03-19-2009 |
20090097315 | Multibit electro-mechanical memory device and method of manufacturing the same - A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites. | 04-16-2009 |
20090115009 | Multibit electro-mechanical memory device and manufacturing method thereof - Provided are a multibit electro-mechanical memory device and a method of manufacturing the same. The device may include at least one bit line in a first direction on a substrate; at least one gate line and at least one lower word line in parallel by a given interval and in a second direction intersecting the first direction on the at least one bit line; at least one contact pad adjacent to the at least one gate line on the at least one bit line; and at least one cantilever electrode coupled to the at least one contact pad, configured to float with a void above and beneath the at least one cantilever electrode and configured to curve in a third direction vertical to the first and second directions. | 05-07-2009 |
20090197383 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths. | 08-06-2009 |
20090237980 | ELECTROMECHANICAL SWITCH AND METHOD OF FORMING THE SAME - A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized. | 09-24-2009 |
20090239346 | SEMICONDUCTOR DEVICE WITH FINFET AND METHOD OF FABRICATING THE SAME - A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided. | 09-24-2009 |
20100012990 | MOSFETS INCLUDING CRYSTALLINE SACRIFICIAL STRUCTURES - A sub-micron channel length MOSFET includes a seamless epitaxial channel region in a substrate of the MOSFET and a buried device isolation layer beneath the seamless epitaxial channel region. In some embodiments according to the invention, a buried device isolation layer includes the buried device isolation layer beneath a central portion of the seamless epitaxial channel and absent from sidewalls of source/drain regions of the MOSFET. | 01-21-2010 |
20100059807 | Semiconductor device having bar type active pattern - A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns. A gate may be arranged to cross the plurality of active patterns in the second direction and to cover a portion of the at least one of the plurality of active patterns. | 03-11-2010 |
20100093146 | METHOD OF MANUFACTURING MULTI-CHANNEL TRANSISTOR DEVICE AND MULTI-CHANNEL TRANSISTOR DEVICE MANUFACTURED USING THE METHOD - A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is formed on the exposed upper side portion of the active region by selective epitaxial growth (SEG). A portion of the active region is selectively etched to define first channel bars in the active expanding region that extend between first and second laterally separated portions of the active region and a second channel bar that is an unetched portion of the active region. A portion of the isolation layer is selectively removed such as to expose side portions of the second channel bar and bottom surface portions of the first channel bars. A gate is formed on the first and second channel bars with a gate dielectric layer between the gate and the channel bars. A source/drain region is formed in a region of the active expanding region adjacent to the gate, thereby resulting in a multi-channel transistor structure. | 04-15-2010 |
20100105181 | METHODS OF FABRICATING VERTICAL TWIN-CHANNEL TRANSISTORS - A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions. | 04-29-2010 |
20100129976 | Methods of Fabricating Electromechanical Non-Volatile Memory Devices - Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern. Related methods are also provided. | 05-27-2010 |
20100135064 | SWITCH AND METHOD OF FORMING THE SAME - A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized. | 06-03-2010 |
20100155827 | Semiconductor device having a multi-channel type MOS transistor - In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor. | 06-24-2010 |
20100197094 | Fin field effect transistor and method of manufacturing the same - Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current. | 08-05-2010 |
20100221876 | FIELD EFFECT TRANSISTORS WITH VERTICALLY ORIENTED GATE ELECTRODES AND METHODS FOR FABRICATING THE SAME - In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device. | 09-02-2010 |
20110006353 | DRAM DEVICES - A DRAM device includes a plug on a substrate, a conductive plate electrically connected to the plug and overlapping the substrate, at least one capacitor on the substrate and spaced apart from the plug, and at least one word line under the conductive plate and spaced apart from the conductive plate. The DRAM device further includes at least one first conductive pad under the conductive plate, the at least one first conductive pad being spaced apart from the conductive plate in a first state and being electrically connected to the conductive plate in a second state, the at least one first conductive pad being disposed between the plug and an adjacent word line of the at least one word line, and the at least one first conductive pad being electrically connected to a respective capacitor of the at least one capacitor. | 01-13-2011 |
20110026243 | BACKLIGHT UNIT AND DISPLAY DEVICE - A backlight unit according to an embodiment includes: a plurality of optical assemblies each including a light source generating light, a light guide plate having a first part through which light travels inside and a second part diffusing upward the light traveling inside through the first part; and a diffusion pattern selectively disposed at the portions corresponding to interfaces between the light guide plates on the optical assemblies. | 02-03-2011 |
20110124194 | METHODS OF MANUFACTURING SEMICONDUCTORS USING DUMMY PATTERNS - A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern. | 05-26-2011 |
20110163940 | OPTICAL ASSEMBLY AND DISPLAY APPARATUS THEREOF - An optical assembly is provided that may include a light emitting module that includes a plurality of light emitting devices to emit light, a light guide plate, and a side cover. The light guide plate may include at least one protrusion on a top surface of a first part of the light guide plate. The side cover includes a plurality of holes to receive the at least one protrusion. | 07-07-2011 |
20110164436 | BACKLIGHT UNIT, AND DISPLAY APPARATUS THEREOF - A backlight unit is provided that may include a plurality of optical assemblies arranged in a matrix form, and a cover to receive the optical assemblies. Each optical assembly may separately include: a light emitting module having a plurality of light emitting devices, a light guide plate, and a cover provided over a portion of the light guide plate. The optical assemblies may include a first optical assembly, a second optical assembly and a third optical assembly. A top surface of the second optical assembly may be spaced from a top surface of the first optical assembly in a first direction by a first interval, and a top surface of the third optical assembly may be spaced from the top surface of the first optical assembly in the second direction by a second interval. | 07-07-2011 |
20110182111 | ELECTROMECHANICAL SWITCH AND METHOD OF FORMING THE SAME - A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized. | 07-28-2011 |
20110189829 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES HAVING STACKED STRUCTURES - A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure. | 08-04-2011 |
20110230001 | MULTIBIT ELECTRO-MECHANICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites. | 09-22-2011 |
20110241980 | BACKLIGHT UNIT AND DISPLAY DEVICE - The embodiments provide a backlight unit including
| 10-06-2011 |
20110242842 | BACK LIGHT UNIT - A back light unit including a light emitting device assembly is disclosed. The light emitting device assembly includes a light emitting device module having a light emitting device, a light guide plate having a light incidence part disposed adjacent to the light emitting device module so that light generated from the light emitting device is incident upon the light incidence part and a light emission part from which the incident light is emitted, a reflective sheet provided at one side of the light guide plate, and a light adjustment part extending from the reflective sheet for adjusting a reflection amount of the light emitted from the light guide plate. | 10-06-2011 |
20110260136 | Semiconductor Devices Including a Transistor With Elastic Channel - A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region. | 10-27-2011 |
20110286202 | BACKLIGHT UNIT AND DISPLAY APPARATUS USING THE SAME - A backlight unit and a display apparatus using the same are disclosed. The backlight unit includes an optical member, a reflector spaced apart from the optical member and having an inclined surface, a fixture connected to one side of the reflector so as to fix the reflector, and a light source disposed to one side of the reflector. | 11-24-2011 |
20110305004 | BACKLIGHT UNIT AND DISPLAY APPARATUS USING THE SAME - Disclosed herein are a backlight unit and a display apparatus using the same. The backlight unit includes at least one light source, a reflection layer to reflect light emitted from the light source, and a plurality of absorption patterns formed on a portion of the reflection layer adjacent to a light emitting surface of the light source, to partially absorb the light emitted from the light source. | 12-15-2011 |
20120014131 | LIGHT EMITTING DEVICE ASSEMBLY, BACKLIGHT UNIT AND DISPLAY DEVICE HAVING THE SAME - Disclosed herein are a light emitting device assembly, a backlight unit and a display device having the same. The light emitting device assembly includes a light emitting device module having a light emitting device disposed on a board, a light guide plate to emit light incident from the light emitting device module in a direction differing from a light incidence direction, and a first fixing cover and a second fixing cover to connect the light emitting device module and the light guide plate. The first fixing cover and the second fixing cover are coupled by fixing members, protrusions are disposed on the second fixing cover at first regions corresponding to the fixing members, and the edge of the second fixing cover at second regions is bent. | 01-19-2012 |
20120140443 | BACKLIGHT UNIT AND DISPLAY APPARATUS USING THE SAME - The backlight unit includes a plurality of light source groups, each of which includes at least one light source, and a light guide plate to guide light irradiated from the plurality of light source groups, and the light guide plate includes first grooves disposed in a first direction, the plurality of light source groups being disposed within the first grooves, and at least one second groove disposed in a second direction differing from the first direction. | 06-07-2012 |
20120161247 | Gate-All-Around Integrated Circuit Devices and Methods of Manufacturing the Same - Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region. | 06-28-2012 |
20120327682 | BACKLIGHT UNIT AND DISPLAY APPARATUS USING THE SAME - Disclosed are a backlight unit and a display apparatus using the same. The backlight unit includes a light guide plate, grooves disposed in the light guide plate, the grooves having at least one inclined surface, light source modules disposed within the grooves, and stoppers disposed between the light source modules and the light guide plate, wherein a cross-sectional area of the grooves is larger than that of the stoppers. The stoppers contact at least one of the side surfaces of the grooves, the bottom surfaces of the grooves and the light source modules. | 12-27-2012 |
20150023058 | BACKLIGHT UNIT AND DISPLAY APPARATUS USING THE SAME - Disclosed are an illumination system and a display apparatus using the same. The illumination system includes a light guide plate; grooves disposed in the light guide plate, each of the grooves having at least one inclined surface; light source modules disposed within the grooves, wherein the light source modules comprise, substrates and light sources disposed on the substrates; and stoppers disposed between a first surface of each of the light sources and the at least one inclined surface of each of the grooves, the first surface of each of the light sources facing the at least one inclined surface. A cross-sectional area of the grooves is larger than that of the stoppers. | 01-22-2015 |