Min-Cheng
Min-Cheng Chan, Taichung City 42084 TW
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20140362822 | SYSTEM ARCHITECTURE AND METHOD FOR SERVICE CONTINUITY IN HETEROGENEOUS WIRELESS NETWORK - The present invention provides a system architecture and a method for service continuity in heterogeneous wireless networks, which comprises a handover decision module and a session continuity module. The handover decision module is responsible for maintaining link layer association and network layer reachability in according to the underlying network conditions to fulfill the service requirement of applications. When acting as a sender, the session continuity module will select transmission path(s), reestablish the transport connection(s) and tag packets with session IDs and sequence numbers. When acting as a receiver, the session continuity module will identify and reorder packets using session IDs and sequence numbers, regardless of the IP addresses and ports of the packets. To sum up, the present invention can provide service continuity and multipath transmission for network devices. | 12-11-2014 |
Min-Cheng Chen, Taipei TW
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20130161755 | THIN FILM TRANSISTOR AND FABRICATING METHOD - A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed. | 06-27-2013 |
20140099756 | THIN FILM TRANSISTOR AND FABRICATING METHOD - A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed. | 04-10-2014 |
Min-Cheng Chen, Hsinchu TW
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20140131716 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device comprises a substrate, a tunnel oxide layer, a charge trapping layer, a block oxide layer, a plurality of conductive quantum dots, a metal gate and a source/drain structure. The tunnel oxide layer is disposed on the substrate and has a thickness substantially less than or equal to 2 nm. The charge trapping layer is disposed on the tunnel oxide layer. The quantum dots are embedded in the charge trapping layer. The block oxide layer is disposed on the charge trapping layer. The metal gate essentially consisting of aluminum (Al), copper (Cu), tantalum nitride (TiN), titanium nitride (TaN), aluminum-silicon-copper (Al—Si—Cu) alloys or the arbitrary combinations thereof is disposed on the block oxide layer. The source/drain structure is disposed in the substrate. | 05-15-2014 |
Min-Cheng Chen, Hsinchu City TW
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20120146161 | NANOWIRE FABRICATION METHOD AND SEMICONDUCTOR ELEMENT USING NANOWIRE FABRICATED THEREBY - The present invention discloses a nanowire fabrication method and a semiconductor element using a nanowire fabricated thereby. The method of the present invention comprises steps: providing a substrate; sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate; forming a patterned photoresist layer on the silicon nitride layer; using the patterned photoresist layer as a mask to etch the silicon nitride layer and the silicon dioxide layer with the substrate partly etched away to form a protrusion; removing the patterned photoresist layer to form an isolation layer; removing the silicon nitride and the silicon dioxide layer, sequentially depositing a dielectric layer and a polysilicon layer; and anisotropically etching the polysilicon layer to form nanowires on a region of the dielectric layer, which is around sidewalls of the protrusion. | 06-14-2012 |
Min-Cheng Huang, Taipei County TW
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20140177156 | Shearing Mechanism for Cutting Through an Adhesive Bonding of a Direct Bonding Panel - An information handling system display having a first part that includes a display screen and rendering electronics fastened onto a second part to seal the rendering electronics within the display. The first part is bonded onto the second part via an adhesive that forms a bond between the two parts. A shearing mechanism is also disposed within the display with at least one externally exposed end. A pulling force is applied to the at least one externally exposed end in order to cut through the bond when there is a need to separate the two parts from each other. | 06-26-2014 |
Min-Cheng Pan, Keelung TW
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20100224782 | Scanning device of multi-point simultaneous acquisition through diffuse optical tomography - A scanning device processes a multi-point simultaneous acquisition. The acquisition is processed for an infra-red diffuse optical tomography. An intensity modulated light is used with a frequency domain analysis theorem to obtain a reconstructed scanning image. The fibers are capable of a vertical movement and a radial movement. Thus, a precise image showing optical-information data is obtained with a low cost, even through scanning at a minimal angle. | 09-09-2010 |
Min-Cheng Tseng, Taoyuan-Hsien TW
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20130084178 | FAN ASSEMBLY STRUCTURE - A fan assembly structure is provided. The fan assembly structure comprises a fan, an air-flow guiding structure and a fixing component. The air-flow guiding structure has a plurality of air-flow guiding holes, a leaning portion and a plurality of first locking portions distributed on the leaning portion. The fixing component has a plurality of second locking portions. The fan is pivotally connected with the fixing component. The second locking portion is adapted to rotate by an angle with respect to the leaning portion to lock with the corresponding first locking portion. Thereby, the fan is disposed on the air-flow guiding structure by only the fixing component. | 04-04-2013 |
Min-Cheng Tseng, Nantou City TW
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20140109731 | PLIERS FOR C-SHAPED LOCK RINGS - Pliers for C-shaped lock rings include a holding unit and a clamping unit. The holding unit is composed of two handles and a control portion. The clamping unit comprises two identical clamping members and a positioning disk. When the control portion is released to engage with the positioning slot to lock the handle; when the control portion is pushed to disengage with the positioning slot, the handle rotate around the center shaft corresponding to the rotations of the clamping unit, such that the clamping members can be open or closed. | 04-24-2014 |
Min-Cheng Wang, Taipei TW
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20100151554 | ENZYME COMPOSITION AND USE THEREFORE - The present invention provides an enzyme composition and a method for treating coal using the enzyme composition. The enzyme composition includes at least one enzyme, coenzyme and ammonium acetate, wherein the enzyme can be laccase-isozyme, pyruvate dehydrogenase, dihydrolipoyl transacetylase, and dihydrolipoyl dehydrogenase, and the coenzyme can be CoA, CoA-SH, thiamine pyrophosphate, lipoic acid, flavin adenine dinucleotide, and nicotinamide adenine dinucleotide. In addition, the method of the present invention includes treating the coal with the enzyme composition for more than 72 hours. | 06-17-2010 |
Min-Cheng Wang, Zhonghe City TW
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20120105776 | LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR FORMING LIQUID CRYSTAL LAYER THEREOF - A liquid crystal display panel includes a transistor array substrate, a color filter substrate, a liquid crystal layer, and a sealant material. The transistor array substrate includes a transparent substrate, a transistor array, and a plurality of peripheral wires. The transparent substrate has a display region and a non-display region, and the non-display region is located beside the display region. The transistor array is disposed in the display region. The peripheral wires are disposed in the non-display region and electrically connected with the transistor array. A transmittance of the non-display region is less than 30%. The liquid crystal layer is disposed between the color filter substrate and the transistor array substrate. The sealant material is disposed in the non-display region and connected between the color filter substrate and the transistor array substrate. The sealant material surrounds the liquid crystal layer. | 05-03-2012 |
Min-Cheng Wang, Miao-Li County TW
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20110252630 | METHOD AND APPARATUS FOR MANUFACTURING BACKLIGHT SOURCE - A manufacturing apparatus for a backlight unit includes a feed mechanism, a testing mechanism, and an attachment mechanism. The feed mechanism arranges a plurality of light-emitting diodes in a row. The testing mechanism tests the light-emitting diodes. The attachment mechanism positions the light-emitting diodes to a circuit board. The attachment mechanism comprises a support assembly and a laminating device, in which the support assembly receives the light-emitting diodes tested by the at least one testing unit, the support assembly is opposite to the circuit board, and the laminating device laminates the light-emitting diodes to the circuit board. A method for manufacturing the backlight unit is also provided. | 10-20-2011 |
Min-Cheng Wang, Miaoli TW
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20100241914 | CONTROLLER HAVING FLASH MEMORY TESTING FUNCTIONS, AND STORAGE SYSTEM AND TESTING METHOD THEREOF - A flash memory controller having a flash memory testing functions is provided, in which the flash memory controller includes a microprocessor unit, a flash memory interface unit, a host interface unit and a memory cell testing unit. The flash memory interface unit is configured for connecting a plurality of flash memory chips, where each flash memory chip has a plurality of flash memory dies and each flash memory die has a plurality of physical blocks. The host interface unit is configured for connecting a host system. The memory cell testing unit is configured for determining whether the physical blocks can be normally written, read and erased. Accordingly, the flash memory controller can perform a flash memory testing under a command of the host system and all the physical blocks of the flash memory chip can be tested during the flash memory testing. | 09-23-2010 |