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| 20080204207 | Two-Way Automotive Remote Controller - A two-way automotive remote control system for a vehicle having a data bus includes a factory enhancement module, a wire harness adapted to connect the factory enhancement module with the data bus of the vehicle, an antenna, and a remote communicating with the factory enhancement module electronically. The factory enhancement module has a data bus interface, a microcontroller, an antenna interface, and a power supply, and activates the remote in predetermined situations of the vehicle. The data bus interface of the factory enhancement module and the antenna interface are monitored continually. The factory enhancement module accepts and decodes the outputs from the alarm system of the vehicle through the data bus interface. The outputs from the alarm system includes messages according to a predetermined communication standard, which includes J1850. The factory enhancement module accepts and decodes predetermined command messages from the remote in an electromagnetic wave transmission. | 08-28-2008 |
| 20110244846 | Cell Phone with Remote Control System - A remote control system includes a mobile phone, a mobile communication network, a plurality of remote systems, and a server. The mobile phone has an antenna, a mobile communication modem, a processing unit, a system memory, a battery, a keypad, a speaker, and a display The mobile communication network comprises a wireless communication network. The remote systems communicate electronic signals with the mobile phone via the mobile communication network. And, the server is connected to the mobile communication network. The mobile phone controls the behavior of the remote system and communicates electronic signals for data, audio, and video with the processing unit having control software programs. The mobile phone decodes the electronic signals and plays on the display and the speaker. The remote mobile phone downloads and installs the control software programs from the server through the mobile communication network. | 10-06-2011 |
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| 20090296794 | System and Method for Performing Ranging in a Cable Modem System - The present invention provides a system and method for performing ranging operations in a cable modem system. In accordance with embodiments of the present invention, transmission times, transmission power levels, transmission carrier frequencies, and pre-equalization parameters are adjusted to provide for robust operation of the cable modem system. More particularly, iterative processing steps are used to provide coefficient ordering, scaling, and aligning between the multiple cable modems and the cable modem termination system present in a cable modem system. | 12-03-2009 |
| 20110013534 | Receiver Having Integrated Spectral Analysis Capability - A method of managing traffic in a communications channel includes the steps of receiving a subscriber ID corresponding to a subscriber, performing a spectral analysis on a signal received from the subscriber within a time interval identified by the subscriber ID, and adjusting transmission characteristics of the subscriber based on the spectral analysis. | 01-20-2011 |
| 20110026423 | Robust Techniques for Upstream Communication Between Subscriber Stations and a Base Station - A number of features for enhancing the performance of a communication system, in which data is transmitted between a base station and a plurality of subscriber stations located different distances from the base station, are presented. The power transmission level, slot timing, and equalization of the subscriber stations are set by a ranging process. Data is transmitted by the subscriber stations in fragmented form. Various measures are taken to make transmission from the subscriber stations robust. The uplink data transmission is controlled to permit multiple access from the subscriber stations. | 02-03-2011 |
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| 20080232440 | CHIP BLANKING AND PROCESSING IN SCDMA TO MITIGATE IMPULSE AND BURST NOISE AND/OR DISTORTION - A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication. | 09-25-2008 |
| 20090285343 | SYSTEM AND METHOD FOR CANCELING INTERFERENCE IN A COMMUNICATION SYSTEM - A filter settings generation operation includes sampling a communication channel to produce a sampled signal. The sampled signal is spectrally characterized across a frequency band of interest to produce a spectral characterization of the sampled signal. This spectral characterization may not include a signal of interest. The spectral characterization is then modified to produce a modified spectral characterization. Filter settings are then generated based upon the modified spectral characterization. Finally, the communication channel is filtered using the filter settings when the signal of interest is present on the communication channel. In modifying the spectral characterization, pluralities of spectral characteristics of the spectral characterization are independently modified to produce the modified spectral characterization. Modifications to the spectral characterization may be performed in the frequency domain and/or the time domain. One particular spectral modification that is performed is raising of the noise floor of the spectral characterization to meet a budgeted signal-to-noise ratio. Other spectral modifications include modifying spectral components corresponding to an expected interfering signal. In modifying these spectral characterizations, spectral components corresponding to a plurality of expected interfering signals may be modified. | 11-19-2009 |
| 20100180165 | SYSTEM AND METHOD OF UNCORRELATED CODE HOPPING IN A COMMUNICATIONS SYSTEM - A system and method are used to provide uncorrelated code hopping in a communications system. A shift register receives data. The shift register is clocked to shift the data. A scaler performs a scaling operation on the data with a numerical value of active codes. A truncator truncates the scaled data to its seven most significant bits to produce a pseudo random hop number. A code matrix shifter circularly shifts the active codes in a code matrix based on the pseudo random hop number to produce a circularly shifted code. A transmitter transmits the circularly shifted code. | 07-15-2010 |
| 20100229075 | CHIP BLANKING AND PROCESSING IN SCDMA TO MITIGATE IMPULSE AND BURST NOISE AND/OR DISTORTION - A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication. | 09-09-2010 |
| 20110135044 | System and Method for Canceling Interference in a Communication System - A filter settings generation operation includes sampling a communication channel to produce a sampled signal. The sampled signal is spectrally characterized across a frequency band of interest to produce a spectral characterization of the sampled signal. This spectral characterization may not include a signal of interest. The spectral characterization is then modified to produce a modified spectral characterization. Filter settings are then generated based upon the modified spectral characterization. Finally, the communication channel is filtered using the filter settings when the signal of interest is present on the communication channel. In modifying the spectral characterization, pluralities of spectral characteristics of the spectral characterization are independently modified to produce the modified spectral characterization. Modifications to the spectral characterization may be performed in the frequency domain and/or the time domain. One particular spectral modification that is performed is raising of the noise floor of the spectral characterization to meet a budgeted signal-to-noise ratio. Other spectral modifications include modifying spectral components corresponding to an expected interfering signal. In modifying these spectral characterizations, spectral components corresponding to a plurality of expected interfering signals may be modified. | 06-09-2011 |
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| 20090051572 | MAPPING ALPHABETIC CHARACTERS TO A NUMERIC KEYPAD - A keypad comprising a plurality of numerically labeled keys; wherein each key on a numeric keypad as mapped to letters of alphabet in a language, wherein a plurality of alphabetic letters are assigned to at least one key on the numeric keypad; wherein a first alphabetic letter is selected from among the plurality of alphabetic letters assigned to the key, in response to a first interaction with said key, such that the first alphabetic letter is the first most frequently used letter from among said plurality of letters assigned to the key in said language. | 02-26-2009 |
| 20090280828 | ACCESS PROBE ENHANCEMENTS - A method of providing a location based service to an access terminal in a mobile communication system is provided. The method includes transmitting one or more access probes, each of the one or more access probes including a preamble having a first specific length and transmitted at a first power level, where the preamble is utilized to determine a position of the access terminal. | 11-12-2009 |
| 20100060514 | NETWORK ASSISTED POSITIONING - A method for acquiring positioning information includes receiving downlink data in a plurality of downlink slot frames, and receiving at a mobile terminal within one of the downlink slot frames, broadcasted global positioning system (GPS) orbital description data. The GPS orbital description data information relates to a first group of orbiting satellites within operable range of the base station (BS) providing the broadcasting of the GPS orbital description data. The method further includes performing GPS-based positioning for the mobile terminal based upon signaling received from a second group of a plurality of orbiting satellites in conjunction with the GPS orbital description data, such that at least one of the second group of the plurality of orbiting satellites is the same as some or all of the orbiting satellites of the first group. | 03-11-2010 |
| 20100062793 | MOBILE STATION ASSISTED LOCATION BASED SERVICE - A method for determining a location of a mobile station is provided. The mobile station is requested to identify pilot signals monitored by the mobile station. A pilot signal report is received from the mobile station identifying the pilot signals monitored. It is determined that a location of the mobile station cannot be determined according to the identified pilot signals. A resource allocation signal is transmitted to the mobile station. A report is received from at least one assisting station. The report includes information for determining the location of the mobile station. The location of the mobile station is determined according to the information received in the report from the at least one assisting station and the signal received at the base station from the mobile station. | 03-11-2010 |
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| 20090001443 | NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC - Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed. | 01-01-2009 |
| 20090057744 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 03-05-2009 |
| 20090242961 | RECESSED CHANNEL SELECT GATE FOR A MEMORY DEVICE - A memory device comprising one or more recessed channel select gates and at least one charge trapping layer. | 10-01-2009 |
| 20090283817 | FLOATING GATE STRUCTURES - Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon. | 11-19-2009 |
| 20090321809 | GRADED OXY-NITRIDE TUNNEL BARRIER - Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed. | 12-31-2009 |
| 20100197131 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 08-05-2010 |
| 20120032252 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 02-09-2012 |
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| 20090111265 | SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 04-30-2009 |
| 20090140325 | FORMING METAL-SEMICONDUCTOR FILMS HAVING DIFFERENT THICKNESSES WITHIN DIFFERENT REGIONS OF AN ELECTRONIC DEVICE - A method of forming an electronic device is provided that includes selectively implanting ions into a workpiece, wherein ions are implanted into a first region of the workpiece that includes a semiconductor material, while substantially none of the ions are implanted into a second region of the workpiece that also includes a semiconductor material. The method further includes depositing a metal-containing film over the first region and the second region after selectively implanting, and then reacting the metal-containing film with the semiconductor material to form a first metal-semiconductor film within the first region and a second metal-semiconductor film within the second region. The first metal-semiconductor film has a first thickness and the second metal-semiconductor film has a second thickness that is different from the first thickness. | 06-04-2009 |
| 20100099249 | SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 04-22-2010 |
| 20110175158 | DUAL CHARGE STORAGE NODE MEMORY DEVICE AND METHODS FOR FABRICATING SUCH DEVICE - A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers. | 07-21-2011 |
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| 20080237683 | HIGH-K TRILAYER DIELECTRIC DEVICE AND METHODS - Methods and structures are described for reducing a gate leakage current and increasing gate coupling ratio in a semiconductor device. In some embodiments, nitride layers are used to limit the oxidation of adjacent silicon gate regions due to oxygen in an intermediate insulator. In various embodiments, the intermediate insulator includes a high-κ dielectric material. Apparatus according to embodiments of the invention are also disclosed. | 10-02-2008 |
| 20080237691 | SELF-ALIGNED CHARGE-TRAPPING LAYERS FOR NON-VOLATILE DATA STORAGE, PROCESSES OF FORMING SAME, AND DEVICES CONTAINING SAME - A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device. | 10-02-2008 |
| 20090097320 | Memory Cells, Electronic Systems, Methods Of Forming Memory Cells, And Methods of Programming Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones. | 04-16-2009 |
| 20090146126 | PROBE-BASED MEMORY - Apparatuses, a method, and a system for a non-volatile, probe-based memory device are disclosed herein. In various embodiments, probe-based memory may be one-time programmable or rewritable nonvolatile probe-based memory. | 06-11-2009 |
| 20090273016 | NANOCRYSTAL FORMATION USING ATOMIC LAYER DEPOSITION AND RESULTING APPARATUS - Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures. | 11-05-2009 |
| 20100176432 | Memory Cells, Methods Of Forming Dielectric Materials, And Methods Of Forming Memory Cells - Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material. | 07-15-2010 |
| 20110133268 | Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones. | 06-09-2011 |
| 20110147827 | Flash memory with partially removed blocking dielectric in the wordline direction - The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction. | 06-23-2011 |
| 20110220989 | Memory Cells, Methods Of Forming Dielectric Materials, And Methods Of Forming Memory Cells - Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material. | 09-15-2011 |
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| 20080272422 | Transistor Providing Different Threshold Voltages and Method of Fabrication Thereof - A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor. | 11-06-2008 |
| 20080272828 | Method and system for adaptive power management - A system comprises an integrated circuit comprising one or more transistors that receive a supply voltage. The system also includes a reference transistor operable to receive a constant current and produce a reference voltage that varies according to temperature or process variations, wherein the reference transistor behaves similarly to at least one of the one or more transistors with respect to temperature or process variations. The system also includes a comparator operable to compare the reference voltage with the received supply voltage and produce an output based at least in part on the difference between the reference voltage and the received supply voltage. The system further includes a controller operable to adjust the received supply voltage based at least in part on the output of the comparator. | 11-06-2008 |
| 20090024377 | System and Method for Modeling Semiconductor Devices Using Pre-Processing - A system for modeling a semiconductor device comprises a pre-processing module and a simulation module. The pre-processing module stores at least one virtual model equation associated with at least one terminal of a semiconductor device. The pre-processing module receives an actual voltage value associated with the at least one terminal. The pre-processing module then calculates at least one modified voltage value for the at least one terminal based at least in part upon the virtual model equation and the actual voltage value. The simulation module receives the modified voltage value, and generates a simulation result for the semiconductor device based at least in part upon the modified voltage value. | 01-22-2009 |
| 20090134475 | Transistor Providing Different Threshold Voltages and Method of Fabrication Thereof - A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor. | 05-28-2009 |
