Patent application number | Description | Published |
20130013566 | STORAGE GROUP SYNCHRONIZATION IN DATA REPLICATION ENVIRONMENTS - A method for dynamically synchronizing storage groups in a data replication environment is disclosed. In one embodiment, such a method includes detecting the addition of a volume to a storage group of a primary storage system. The method then automatically performs the following in response to detecting the addition of the volume: (1) adds a corresponding volume to a corresponding storage group on a secondary storage system; (2) creates a mirroring relationship between the volume added to the primary storage system and the volume added to the secondary storage system; and (3) adds the mirroring relationship to a mirroring session established between the storage groups on the primary and secondary storage systems. A corresponding system and computer program product are also disclosed. | 01-10-2013 |
20130326051 | PERFORMANCE ANALYSIS USING ANONYMOUS AGGREGATED DATA - An approach to improving performance of a target system is disclosed. The approach may involve determining how similar a target system being considered is to other systems in use by other clients. For each of these other separate systems, the approach may involve determining the differences between the performance of the target system and the performance of the separate system, accounting for the level of similarity. A report can be generated that identifies performance values of the target system that are outside an acceptable range, which is based on the performance of the other separate systems. Based on this report, the administrator of the target system can consider configuration changes and upgrades to improve performance of the target system. | 12-05-2013 |
20150186070 | MIGRATING HIGH ACTIVITY VOLUMES IN A MIRROR COPY RELATIONSHIP TO LOWER ACTIVITY VOLUME GROUPS - Provided are a computer program product, system, and method for migrating high activity volumes in a mirror copy relationship to lower activity volume groups. A determination is made of usage rates of multiple volume groups, wherein each volume group is comprised of source volumes at a primary site whose data is copied to volumes at a secondary site. A first selected volume group and a second selected volume group are selected based on the determined usage rates of the volume groups. A first volume in the first selected volume group is migrated to a second volume in the second selected volume group. Updates to the first volume, received while migrating the first volume to the second volume, are copied to a mirror first volume mirroring the first volume at the secondary site. | 07-02-2015 |
20150324280 | FLASH COPY RELATIONSHIP MANAGEMENT - For flash copy relationship management, a management module identifies a data unit in a flash copy relationship with an extent range using a flash copy table. A resolution module erases the flash copy relationship from the flash copy table in response to the flash copy relationship completing. | 11-12-2015 |
Patent application number | Description | Published |
20090184655 | POWER MANAGEMENT SYSTEM FOR LIGHT EMITTING DIODES - A power management system comprising: providing a one pin driver circuit; sourcing a managed current from the one pin driver circuit; and illuminating a light emitting diode by the managed current including reducing the managed current when the light emitting diode is not coupled. | 07-23-2009 |
20100007316 | Current Sensing In a Buck-Boost Switching Regulator Using Integrally Embedded PMOS Devices - A current sense device for a power transistor is described. The power transistor is formed in a cellular structure including a cellular array of transistor cells. The current sense device includes multiple transistor cells in the cellular array of transistor cells of the power transistor being used as sense transistor cells. The sense transistor cells are evenly distributed throughout the cellular array where the source terminal of each sense transistor cell is electrically connected to a first node through a metal line in the first metal layer and through a metal line in the second metal layer where the metal lines are electrically isolated from the metal lines connecting the transistor cells of the power transistor. The sense transistor cells measure a small portion of the current flowing through the power transistor based on the size ratio of the current sense device and the power transistor. | 01-14-2010 |
20100271078 | CIRCUITRY IN A DRIVER CIRCUIT - A driver circuit includes a first and a second voltage rail, a first pre-driver circuit, a power transistor, comparison circuitry which indicates when a voltage level of the first voltage rails is above or below a reference voltage level, a level shift circuit coupled between the first voltage rail and the second voltage rail which provides a level shifted output, a tapered buffer circuit coupled to the first voltage rail and to a first circuit node, wherein the tapered buffer circuit receives the level shifted output and provides a buffered output to a control electrode of the first pre-driver transistor, and a rail voltage adjusting circuit coupled between the first circuit node and the second voltage rail, which, in response to the comparison circuitry indicating that the voltage level of the first voltage rail is above the reference voltage level, adjusts a voltage level of the second voltage rail. | 10-28-2010 |
20110309812 | SWITCHING REGULATOR WITH INPUT CURRENT LIMITING CAPABILITIES - A switching regulator includes a capacitor, a charge control circuit, a discharge detector, a switch circuit, and a feedback circuit. The charge control circuit charges and discharges the capacitor. The discharge detector has an input coupled to the capacitor to detect when the capacitor has discharged to a predetermined level to indicate an over-current condition. The switch circuit is coupled to receive an input voltage. The switch circuit is made conductive and non conductive by a switching signal for supplying an output voltage at a regulated voltage level. The duty cycle of the switching signal is reduced in response to an indication of an over-current condition. The feedback circuit is for controlling a discharge rate of the capacitor. | 12-22-2011 |
20110309873 | CIRCUIT HAVING GATE DRIVERS HAVING A LEVEL SHIFTER - A circuit comprises a first level shifting circuit. The level shifting circuit comprises a first and second latching differential pairs. The first latching differential pair has first and second inputs for receiving first and second input signals, first and second outputs, and first and second power supply voltage terminals for receiving a first power supply voltage. The second latching differential pair has first and second inputs coupled to the first and second outputs of the first latching differential pair, an output, and first and second power supply voltage terminals for receiving a second power supply voltage, the second power supply voltage being different from the first power supply voltage. In one embodiment, the level shifting circuit protects transistor gates of the circuit from an overvoltage. | 12-22-2011 |
20140266385 | DUAL SUPPLY LEVEL SHIFTER CIRCUITS - A dual supply level shifter circuit includes a switching circuit and a set of level shifter circuits coupled to the switching circuit. The switching circuit includes a first set of coupled transistors, wherein the supply switching circuit is coupled to a first supply source that is configured to provide a first power supply voltage and is coupled to a second supply source that is configured to provide a second power supply voltage. The set of level shifter circuits includes a second set of coupled transistors, wherein the set of level shifter circuits is configured to receive a voltage input signal at an input node from a first circuit and to supply to an output node of the dual supply level shifter circuit an output signal having a value that is a highest voltage value between the first power supply voltage and the second power supply voltage. | 09-18-2014 |
Patent application number | Description | Published |
20080243522 | APPARATUS, SYSTEM, AND METHOD FOR PARALLELIZING ACCESS TO SHARED ASSESTS - An apparatus, system, and method are disclosed for parallelizing access to shared assets. A size module determines if a size of a first spoke of a plurality of spokes is greater than a low threshold. The spokes are arranged in a circular order wherein a global spoke pointer identifies the first spoke as a current spoke. Each spoke is configured as an asset queue. A request module requests an asset from the first spoke if the size of the first spoke is greater than the low threshold. A rotate module rotates the global spoke pointer to a second spoke of the plurality of spokes if the size of the first spoke is not greater than the low threshold, wherein the second spoke becomes the current spoke. | 10-02-2008 |
20090064159 | SYSTEM AND METHOD FOR OPTIMIZING LOAD DISTRIBUTION ACROSS LOGICAL AND PHYSICAL RESOURCES IN A STORAGE SYSTEM - An apparatus, system and method to optimize load distribution across logical and physical resources in a storage system. An apparatus in accordance with the invention may include an availability module and an allocation module. The availability module may dynamically assign values to resources in a hierarchical tree structure. Each value may correspond to an availability parameter such as allocated volumes, current resource utilization, and historic resource utilization. The allocation module may serially process the values and allocate a load to a least busy resource in the hierarchical tree structure based on the assigned values. | 03-05-2009 |
20090293063 | MINIMIZATION OF READ RESPONSE TIME - A method, system and computer program product for minimizing read response time in a storage subsystem including a plurality of resources is provided. A middle logical block address (LBA) is calculated for a read request. A preferred resource of the plurality of resources is determined by calculating a minimum seek time based on a closest position to a last position of a head at each resource of the plurality of resources, estimated from the middle LBA. The read request is directed to at least one of the preferred resource or an alternative resource. | 11-26-2009 |
Patent application number | Description | Published |
20100075634 | TELEPHONY APPARATUS - A system and methods through which incoming calls to and/or outgoing calls from a telephone can be controlled. The present invention utilizes an authorized caller list to determine whether an incoming call should be connected, and a similar list to determine whether an outgoing call should be connected. The present invention can also facilitate the use of new telephone user interfaces, including by iterating through telephone numbers associated with a contact, until communications with the contact are established. | 03-25-2010 |
20110092187 | CONFIGURABLE PHONE WITH INTERACTIVE VOICE RESPONSE ENGINE - A land-based or mobile phone and methods are provided for receiving inbound communications as either voice or text, and then based on the user's configuration settings, the inbound communication is provided to the user as it was received or is automatically converted into a format that is desired by the user. The phone also takes voice or text that is input by the user of the phone and converts the user's input to either voice or text based on the configuration settings stored in the user's contact list or otherwise. The outbound communication is configured according to how the intended recipient wants to receive a communication based on the configuration settings stored in the user's contact list or otherwise. The phone includes a controller that determines how the phone will handle and process inbound and outbound communications. The controller includes a speech recognition engine. | 04-21-2011 |
20140187225 | CONFIGURABLE PHONE WITH INTERACTIVE VOICE RESPONSE ENGINE - A land-based or mobile phone and methods are provided for receiving inbound communications as either voice or text, and then based on the user's configuration settings, the inbound communication is provided to the user as it was received or is automatically converted into a format that is desired by the user. The phone also takes voice or text that is input by the user of the phone and converts the user's input to either voice or text based on the configuration settings stored in the user's contact list or otherwise. The outbound communication is configured according to how the intended recipient wants to receive a communication based on the configuration settings stored in the user's contact list or otherwise. The phone includes a controller that determines how the phone will handle and process inbound and outbound communications. The controller includes a speech recognition engine. | 07-03-2014 |
Patent application number | Description | Published |
20090204764 | Cache Pooling for Computing Systems - In a computing system a method and apparatus for cache pooling is introduced. Threads are assigned priorities based on the criticality of their tasks. The most critical threads are assigned to main memory locations such that they are subject to limited or no cache contention. Less critical threads are assigned to main memory locations such that their cache contention with critical threads is minimized or eliminated. Thus, overall system performance is improved, as critical threads execute in a substantially predictable manner. | 08-13-2009 |
20100182233 | SYSTEMS AND METHODS FOR DETECTING CURSOR INTERFERENCE IN VISUAL DISPLAYS - A system for detecting cursor interference includes a graphics engine configured to generate graphics information; a first evaluation unit coupled to the graphics engine and configured to evaluate the graphics information; a cursor generation unit coupled to the graphics engine and configured to generate cursor information, the cursor generator further configured to merge the cursor information and the graphics information into merged information; a second evaluation unit coupled to the cursor generation unit and configured to evaluate the merged information; and a display device coupled to the cursor generation unit and configured to display the merged information based on the evaluations of the graphics information and the merged information. | 07-22-2010 |
20100205414 | HIGH INTEGRITY PROCESSOR MONITOR - A method of ensuring high integrity of a processor is provided. The method includes executing sets of sequential instructions, each execution being based on a unique initial value, generating a computed final value responsive to each execution of a set of sequential instructions, and sending computed values to a monitoring portion of a high integrity processor monitor system responsive to the generating for each execution of the set of sequential instructions. The execution of the sets of sequential instructions tests pertinent addressing modes, operand sizes, and instruction side-effects for each instruction tested in a monitored central processing unit. | 08-12-2010 |
20130036421 | CONSTRAINED RATE MONOTONIC ANALYSIS AND SCHEDULING - A method for scheduling schedulable entities onto an execution timeline for a processing entity in a constrained environment includes determining available capacity on the execution timeline for the processing entity based on constraints on the execution timeline over a plurality of time periods, wherein schedulable entities can only be scheduled onto the execution timeline during schedulable windows of time that are not precluded by constraints. The method further includes determining whether enough available capacity exists to schedule a schedulable entity with a budget at a rate. The method further includes when enough available capacity exists to schedule the schedulable entity with the budget at the rate, scheduling the schedulable entity onto the execution timeline for the processing entity during a schedulable window of time. The method further includes when the schedulable entity is scheduled onto the execution timeline, updating available capacity to reflect the capacity utilized by the schedulable entity. | 02-07-2013 |
20130036423 | SYSTEMS AND METHODS FOR BOUNDING PROCESSING TIMES ON MULTIPLE PROCESSING UNITS - Embodiments of the present invention provide improved systems and methods for processing multiple tasks. In one embodiment a method comprises: selecting a processing unit as a master processing unit from a processing cluster comprising multiple processing units, the master processing unit selected to execute master instruction entities; reading a master instruction entity from memory; scheduling the master instruction entity to execute on the master processing unit; identifying an execution group containing the master instruction entity, the execution group defining a set of related entities; when the execution group contains at least one slave instruction entity, scheduling the at least one slave instruction entity to execute on a processing unit other than the master processing unit during the execution of the master instruction entity; and terminating execution of instruction entities related by the execution group when a master instruction entity is executed that is not a member of the execution group. | 02-07-2013 |
20130205301 | SYSTEMS AND METHODS FOR TASK GROUPING ON MULTI-PROCESSORS - Embodiments of the present invention provide improved systems and methods for grouping instruction entities. In one embodiment, a system comprises a processing cluster to execute software, the processing cluster comprising a plurality of processing units, wherein the processing cluster is configured to execute the software as a plurality of instruction entities. The processing cluster is further configured to execute the plurality of instruction entities in a plurality of execution groups, each execution group comprising one or more instruction entities, wherein the processing cluster executes a group of instruction entities in the one or more instruction entities in an execution group concurrently. Further, the execution groups are configured so that a plurality of schedule-before relationships are established, each schedule-before relationship being established among a respective set of instruction entities by executing the plurality of instruction entities in the plurality of execution groups. | 08-08-2013 |
20150205724 | SYSTEM AND METHOD OF CACHE PARTITIONING FOR PROCESSORS WITH LIMITED CACHED MEMORY POOLS - A method comprises dividing a main memory into a plurality of pools, the plurality of pools including a first pool and one or more second pools, wherein the first pool is only associated with a set of one or more lines in a first cache such that data in the first pool is only cached in the first cache and wherein the one or more second pools are each associated with one or more lines in a second cache and data in the second cache is cacheable by the first cache. The method further comprises assigning each of a plurality of threads to one of the plurality of pools and determining if a memory region being accessed belongs to the first pool. If the memory region being accessed belongs to the first pool, bypassing the second cache to temporarily store data from the memory region in the first cache. | 07-23-2015 |
Patent application number | Description | Published |
20130024256 | SYSTEM AND METHOD FOR COUPON-LESS PRODUCT LEVEL DISCOUNTS - A product level discount is managed during a transaction by receiving a transaction identifier associated with a transaction, where the transaction identifier comprises a transaction value, a customer account identifier, a merchant identifier, and a product identifier. A product identifier is assessed to determine whether the transaction qualifies for a rebate credit in accordance with a predetermined offer. A rebate credit value is based on the transaction information and the predetermined offer, and qualification may be determined based on at least one of the customer account identifier and the merchant identifier. The product identifier could be a SKU code, which may be the basis for qualifying for the rebate credit. A merchant associated with the merchant identifier, which is part of the transaction, does not need to be informed of the application of the rebate credit to the customer account, which occurs after completion of the transaction. | 01-24-2013 |
20130024259 | SYSTEM AND METHOD FOR COUPON-LESS PRODUCT LEVEL DISCOUNTS - A product level discount is managed during a transaction by receiving a transaction identifier associated with a transaction, where the transaction identifier comprises a transaction value, a customer account identifier, a merchant identifier, and a product identifier. A product identifier is assessed to determine whether the transaction qualifies for a rebate credit in accordance with a predetermined offer. A rebate credit value is based on the transaction information and the predetermined offer, and qualification may be determined based on at least one of the customer account identifier and the merchant identifier. The product identifier could be a SKU code, which may be the basis for qualifying for the rebate credit. A merchant associated with the merchant identifier, which is part of the transaction, does not need to be informed of the application of the rebate credit to the customer account, which occurs after completion of the transaction. | 01-24-2013 |
Patent application number | Description | Published |
20090152698 | INTEGRATED MATCHING NETWORKS AND RF DEVICES THAT INCLUDE AN INTEGRATED MATCHING NETWORK - An integrated matching network includes a first die on a substrate, a second die on the substrate, and a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a power amplifier, a second die having a capacitor, and a metal interconnect coupled to the power amplifier and the first capacitor. The metal interconnect has an inductance. The capacitor and metal interconnect form a shunt impedance. | 06-18-2009 |
20090218642 | MICROELECTROMECHANICAL SYSTEMS COMPONENT AND METHOD OF MAKING SAME - A microelectromechanical systems (MEMS) component | 09-03-2009 |
20100214716 | MEMS CAPACITIVE DEVICE AND METHOD OF FORMING SAME - A MEMS capacitive device ( | 08-26-2010 |
20130005109 | METHOD FOR FORMING A TOROIDAL INDUCTOR IN A SEMICONDUCTOR SUBSTRATE - A toroidal inductor formed in a semiconductor substrate. Through-silicon vias are used to connect metal layers formed on top and bottom surfaces of the semiconductor substrate. In one embodiment, the vias are elongated and laid out in two concentric circles, an inner circle enclosed by an outer circle. The vias of the outer concentric circle are longer than the vias of the inner circle so that spaces between vias are the same for both circles. In another embodiment, each elongated via may include a plurality of circular vias formed in a line. Metals layers on the top and bottom of the semiconductor substrate are patterned to form wedge shaped connectors between the inner and outer vias to form the spirals of the toroidal inductor. The wedge shaped connectors with elongated vias allow spacing between spirals to be constant. | 01-03-2013 |
Patent application number | Description | Published |
20080310550 | REDUNDANCY SYSTEM FOR A TELECOMMUNICATION SYSTEM AND RELATED METHODS - A redundancy system for a co-channel telecommunication system and related methods. Implementations of the redundancy system may include at least a first modulator and a second modulator having a symbol mapper coupled to a parallel bit signal. The symbol mapper may be configured to route each of a plurality of parallel bits received through the parallel bit signal to a plurality of significant bit signals. In a first implementation, a plurality of significant bit signal multiplexers may be used to switch the plurality of parallel bit signals to allow the first and second modulators to operate in either a redundant or operating mode. In a second implementation, a premapped symbol (PMSI) encoder and a PMSI decoder may be used to transmit the plurality of significant bit signals across an interface bus as a real dual-data rate (DDR) signal and an imaginary DDR signal. | 12-18-2008 |
20090054026 | SIGNAL FILTERING SYSTEM AND RELATED METHODS - A signal filtering system for a frequency reuse system. A first implementation may include a downlink baseband signal, coupled to a downlink bandwidth filter, including a composite received signal including at least an interfering signal and a signal of interest, each having a composite bandwidth, a first bandwidth, and a second bandwidth, respectively. An uplink baseband signal may be included, coupled to an uplink bandwidth filter, having a replica of the interfering signal corresponding with the interfering signal and having an interference bandwidth. A baseband processing module may be coupled with the downlink bandwidth filter and the uplink bandwidth filter and may be configured to cancel the interfering signal from the composite received signal using the replica of the interfering signal. The downlink bandwidth filter may be configured to reduce the composite bandwidth and the uplink bandwidth filter may be configured to reduce the interference bandwidth. | 02-26-2009 |
20110287730 | SIGNAL FILTERING SYSTEM AND RELATED METHODS - A signal filtering system for a frequency reuse system. A first implementation may include a downlink baseband signal, coupled to a downlink bandwidth filter, including a composite received signal including at least an interfering signal and a signal of interest, each having a composite bandwidth, a first bandwidth, and a second bandwidth, respectively. An uplink baseband signal may be included, coupled to an uplink bandwidth filter, having a replica of the interfering signal corresponding with the interfering signal and having an interference bandwidth. A baseband processing module may be coupled with the downlink bandwidth filter and the uplink bandwidth filter and may be configured to cancel the interfering signal from the composite received signal using the replica of the interfering signal. The downlink bandwidth filter may be configured to reduce the composite bandwidth and the uplink bandwidth filter may be configured to reduce the interference bandwidth. | 11-24-2011 |
20120057509 | REDUNDANCY SYSTEM FOR A TELECOMMUNICATION SYSTEM AND RELATED METHODS - A redundancy system for a co-channel telecommunication system and related methods. Implementations of the redundancy system may include at least a first modulator and a second modulator having a symbol mapper coupled to a parallel bit signal. The symbol mapper may be configured to route each of a plurality of parallel bits received through the parallel bit signal to a plurality of significant bit signals. In a first implementation, a plurality of significant bit signal multiplexers may be used to switch the plurality of parallel bit signals to allow the first and second modulators to operate in either a redundant or operating mode. In a second implementation, a premapped symbol (PMSI) encoder and a PMSI decoder may be used to transmit the plurality of significant bit signals across an interface bus as a real dual-data rate (DDR) signal and an imaginary DDR signal. | 03-08-2012 |
Patent application number | Description | Published |
20090098770 | Electrical Connector With Grounding Member - A coaxial cable connector includes tubular post, a coupler secured over an end of the tubular post for securing the connector to an appliance, and an outer body secured to the tubular post. An electrical grounding pat is maintained between the coupler and the tubular post whether or not the coupler is tightly fastened to the appliance. The electrical grounding path is provided by a resilient, electrically-conductive grounding member disposed between the tubular post and the coupler. Alternatively, the connector includes conductive grease at a point where mating portions of the tubular post and coupler have closely matching dimensions. | 04-16-2009 |
20110230090 | ELECTRICAL CONNECTOR WITH GROUNDING MEMBER - A coaxial cable connector includes tubular post, a coupler secured over an end of the tubular post for securing the connector to an appliance, and an outer body secured to the tubular post. An electrical grounding path is maintained between the coupler and the tubular post whether or not the coupler is tightly fastened to the appliance. The electrical grounding path is provided by a resilient, electrically-conductive grounding member disposed between the tubular post and the coupler. Alternatively, the connector includes conductive grease at a point where mating portions of the tubular post and coupler have closely matching dimensions. | 09-22-2011 |
20120270441 | ELECTRICAL CONNECTOR WITH GROUNDING MEMBER - A coaxial cable connector includes tubular post, a coupler secured over an end of the tubular post for securing the connector to an appliance, and an outer body secured to the tubular post. An electrical grounding path is maintained between the coupler and the tubular post whether or not the coupler is tightly fastened to the appliance. The electrical grounding path is provided by a resilient, electrically-conductive grounding member disposed between the tubular post and the coupler. Alternatively, the connector includes conductive grease at a point where mating portions of the tubular post and coupler have closely matching dimensions. | 10-25-2012 |
20140148051 | ELECTRICAL CONNECTOR WITH GROUNDING MEMBER - A coaxial cable connector for coupling a coaxial cable to an equipment port, the coaxial cable including a center conductor surrounded by a dielectric material, the dielectric material being surrounded by an outer conductor, the coaxial cable connector including: a post including a first end adapted to be inserted into a prepared end of the coaxial cable between the dielectric material and the outer conductor, wherein the post includes a second end including an enlarged shoulder, wherein the enlarged shoulder has a radial face that faces away from the first end of the post, wherein the radial face is substantially flat; a body member adjacent to the post; a coupler including an internally-threaded region for engaging the equipment port; and a grounding member contacting the post and the coupler, wherein the grounding member provides an electrically-conductive grounding path through the post and the coupler while allowing the coupler to rotate, wherein the grounding member includes at least one resilient portion. | 05-29-2014 |
Patent application number | Description | Published |
20120171895 | Re-Enterable Hardline Coaxial Cable Connector - A hardline coaxial cable connector includes a body subassembly, a back nut subassembly and a deformable ferrule disposed within the back nut subassembly. The back nut subassembly is rotatable with respect to the body subassembly and a coaxial cable inserted therein. Axial advancement of the back nut subassembly toward the body subassembly causes the ferrule to deform radially inwardly and be in electrical communication with the body subassembly. | 07-05-2012 |
20140106614 | COAXIAL CABLE CONNECTOR WITH A COMPRESSIBLE FERRULE - A coaxial connector for coupling an end of a coaxial cable to a terminal is disclosed. The coaxial cable connector includes a body, a retainer, a coupler, a ferrule, and a shell. The retainer engages the body and rotatably engages the coupler. The ferrule slidingly engages at least a portion of the retainer and at least one portion of the body. The ferrule engages at least a portion of the cable outer conductor. The shell slidingly engages at least a portion of the rear end of the body. A sealing ring engages the rear end of the body. Upon compression of the coaxial cable connector the sealing ring engages the jacket of the coaxial cable. | 04-17-2014 |
20140342605 | COAXIAL CABLE CONNECTOR WITH INTEGRAL RFI PROTECTION - A coaxial cable connector for coupling an end of a coaxial cable to a terminal is disclosed. The connector has a coupler, a body assembled with the coupler, and a post assembled with the coupler and the body. The coupler is adapted to couple the connector and, thereby, the coaxial cable to the terminal. The post is adapted to receive an end of a coaxial cable and has a contacting portion of monolithic construction with the post. The contacting portion extends in a generally perpendicular orientation with respect to a longitudinal axis of the connector, and is configured to maintain the generally perpendicular orientation and facilitate and electrical continuity between the post and the coupler to provide RF shielding such that the integrity of an electrical signal transmitted through coaxial cable connector is maintained regardless of the tightness of the coupling of the connector to the terminal. | 11-20-2014 |
Patent application number | Description | Published |
20090186494 | APPARATUS, SYSTEM, AND METHOD FOR A CONFIGURABLE BLADE CARD - An apparatus, system, and method are disclosed for a configurable blade card. A base card is in physical and electrical communication with a blade connector. The blade connector is in physical and electrical communication with a blade enclosure connector. A secondary card is in physical and electrical communication with the base card to form a blade card. A coupler physically couples the base card and the secondary card. The base card and the secondary card are co-planar and compatible with a blade card form factor. | 07-23-2009 |
20130091509 | OFF-LOADING OF PROCESSING FROM A PROCESSOR BLADE TO STORAGE BLADES - A processor blade determines whether a selected processing task is to be off-loaded to a storage blade for processing. The selected processing task is off-loaded to the storage blade via a planar bus communication path, in response to determining that the selected processing task is to be off-loaded to the storage blade. The off-loaded selected processing task is processed in the storage blade. The storage blade communicates the results of the processing of the off-loaded selected processing task to the processor blade. | 04-11-2013 |
20140347764 | APPARATUS, SYSTEM, AND METHOD FOR OPTIMALLY POSITIONING AN IDLE ROBOTIC ACCESSOR IN A TAPE LIBRARY - In one embodiment, a system includes a robotic accessor for transporting media between multiple storage slots and one or more data storage drives; a controller for controlling the robotic accessor; a memory in communication with and/or integrated with the controller for storing information about the media and the storage slots, the information including data corresponding to a physical distribution of the media in the storage slots; and logic integrated with and/or executable by the controller, the logic being adapted to: position the robotic accessor at a computed optimal position during an idle period of the robotic accessor, the computed optimal position being based at least in part on the physical distribution of the media in the storage slots. | 11-27-2014 |
20150193349 | Cache Prefetching Based on Non-Sequential Lagging Cache Affinity - A mechanism is provided in a cache subsystem for cache prefetching based on non-sequential access. The mechanism determines frequently accessed non-sequential cache records in the cache subsystem. The mechanism collects trailing record statistics for the frequently accessed non-sequential cache records. The mechanism determines a caching strategy. The caching strategy comprises prefetching a set of trailing records responsive to a read of a given frequently accessed non-sequential cache record. The mechanism applies the caching strategy to the cache subsystem. | 07-09-2015 |
20150231783 | OPTIMALLY POSITIONING AN IDLE ROBOTIC ACCESSOR IN A TAPE LIBRARY - In one embodiment, a system includes a controller for controlling a robotic accessor, and a memory in communication with and/or integrated with the controller for storing information about media and storage slots. The information includes data corresponding to a physical distribution of the media in the storage slots. Logic integrated with and/or executable by the controller is configured to position the robotic accessor at a computed optimal position during an idle period of the robotic accessor, the computed optimal position being based at least in part on at least one of: (a) the data corresponding to the physical distribution of the media in the storage slots, and (b) a center of access calculated using the data corresponding to the physical distribution of the media in the storage slots. | 08-20-2015 |
Patent application number | Description | Published |
20090037662 | Method for Selectively Enabling and Disabling Read Caching in a Storage Subsystem - A mechanism for selectively disabling and enabling read caching based on past performance of the cache and current read/write requests. The system improves overall performance by using an autonomic algorithm to disable read caching for regions of backend disk storage (i.e., the backstore) that have had historically low cache hit ratios. The result is that more cache becomes available for workloads with larger hit ratios, and less time and machine cycles are spent searching the cache for data that is unlikely to be there. | 02-05-2009 |
20090064159 | SYSTEM AND METHOD FOR OPTIMIZING LOAD DISTRIBUTION ACROSS LOGICAL AND PHYSICAL RESOURCES IN A STORAGE SYSTEM - An apparatus, system and method to optimize load distribution across logical and physical resources in a storage system. An apparatus in accordance with the invention may include an availability module and an allocation module. The availability module may dynamically assign values to resources in a hierarchical tree structure. Each value may correspond to an availability parameter such as allocated volumes, current resource utilization, and historic resource utilization. The allocation module may serially process the values and allocate a load to a least busy resource in the hierarchical tree structure based on the assigned values. | 03-05-2009 |
20090210727 | APPARATUS AND METHOD TO MANAGE POWER IN A COMPUTING DEVICE - A method to manage power in a computing device comprising a controller assembly and a storage assembly comprising a plurality of data storage devices, by selecting a processor parameter, establishing a threshold processor parameter value, establishing a threshold over-parameter time interval, selecting a data storage device parameter, and establishing a nominal data storage device parameter value. The method determines an actual processor parameter value. If the actual processor parameter value is less than or equal to the threshold processor parameter value, the method operates each of the plurality of data storage devices using the nominal data storage device parameter value. If the actual processor parameter value is greater than the threshold processor parameter value, then the method determines an actual over-parameter time interval. If the actual processor parameter value is greater than the threshold processor parameter value, and if the actual over-parameter time interval is greater than the threshold over-parameter time interval, then the method operates each of the plurality of data storage devices using a data storage device parameter value less than the nominal data storage device parameter value. | 08-20-2009 |
20100186018 | OFF-LOADING OF PROCESSING FROM A PROCESSOR BADE TO STORAGE BLADES - A processor blade determines whether a selected processing task is to be off-loaded to a storage blade for processing. The selected processing task is off-loaded to the storage blade via a planar bus communication path, in response to determining that the selected processing task is to be off-loaded to the storage blade. The off-loaded selected processing task is processed in the storage blade. The storage blade communicates the results of the processing of the off-loaded selected processing task to the processor blade. | 07-22-2010 |