Patent application number | Description | Published |
20100229383 | WAFER LEVEL TEST PROBE CARD - A probe card for wafer level testing of a plurality of semiconductor devices simultaneously. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing. | 09-16-2010 |
20100278211 | METHOD AND SYSTEM OF TESTING A SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device, the device includes a substrate, a front-end structure formed in the substrate, a back-end structure formed on the front-end structure, a heater embedded in the back-end structure and operable to generate heat, and a sensor embedded in the back-end structure and operable to sense a temperature of the semiconductor device. | 11-04-2010 |
20120097944 | TEST STRUCTURES FOR THROUGH SILICON VIAS (TSVs) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) - A plurality of through silicon vias (TSVs) on a substrate or in a 3 dimensional integrated circuit (3DIC) are chained together. TSVs are chained together to increase the electrical signal. A plurality of test pads are used to enable the testing of the TVSs. One of the test pads is grounded. The remaining test pads are either electrically connected to TSVs in the chain or grounded. | 04-26-2012 |
20120133379 | MECHANISMS FOR RESISTIVITY MEASUREMENT OF BUMP STRUCTURES - The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers. | 05-31-2012 |
20120273782 | INTERPOSERS OF 3-DIMENSIONAL INTEGRATED CIRCUIT PACKAGE SYSTEMS AND METHODS OF DESIGNING THE SAME - An interposer of a package system includes a first probe pad disposed adjacent to a first surface of the interposer. A second probe pad is disposed adjacent to the first surface of the interposer. A first bump of a first dimension is disposed adjacent to the first surface of the interposer. The first bump is electrically coupled with the first probe pad. A second bump of the first dimension is disposed adjacent to the first surface of the interposer. The second bump is electrically coupled with the second probe pad. The second bump is electrically coupled with the first bump through a redistribution layer (RDL) of the interposer. | 11-01-2012 |
20130093452 | PROBE CARD PARTITION SCHEME - A method of probe card partitioning for testing an integrated circuit die includes providing a first probe card partition layout having a first number of distinct sections. Each distinct section uses a distinct probe card for testing. The first probe card partition layout is repartitioned into a second probe card partition layout having a second number of distinct sections. The second number is less than the first number. | 04-18-2013 |
20130099809 | METHODS AND SYSTEMS FOR PROBING SEMICONDUCTOR WAFERS - A wafer probing method includes calibrating a wafer probing system, checking continuity between probe pins of the wafer probing system and respective conductors of a wafer under test, and identifying at least an interconnect structure in the wafer under test to determine whether a fault exists. | 04-25-2013 |
20130147505 | TEST PROBING STRUCTURE - A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps. | 06-13-2013 |
20130196458 | METHOD OF TESTING THROUGH SILICON VIAS (TSVS) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) - In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded. | 08-01-2013 |
20140043148 | THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD FOR WIRELESS INFORMATION ACCESS THEREOF - A three-dimensional integrated circuit (3DIC) and wireless information access methods thereof are provided. The proposed 3DIC includes a semiconductor structure, and a wireless power device (WPD) formed on the semiconductor structure for wirelessly receiving a power for operating a function selected from a group consisting of probing the semiconductor structure, testing the semiconductor structure and accessing a first information from the semiconductor structure. | 02-13-2014 |
20140167799 | THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION AND PREVENTION TEST INTERFACE - The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection. | 06-19-2014 |
20140253162 | INTEGRATED CIRCUIT TEST SYSTEM AND METHOD - A system for testing a device under test (DUT) includes a probe card and a test module. The probe card includes probe beds electrically coupled to a circuit board and a first plurality of electrical contacts coupled to the circuit board, which are for engaging respective ones of a plurality of electrical contacts of a test equipment module. Probes are coupled to respective probe beds and are disposed to engage electrical contacts of the DUT. The probe card includes a second plurality of electrical contacts coupled to the circuit board. The first and second pluralities of contacts are mutually exclusive. The test module includes a memory, a processor, and a plurality of electrical contacts electrically coupled to respective ones of the second plurality of electrical contacts of the probe card. The circuit board includes a first electrical path for electrically coupling the test equipment module to the test module. | 09-11-2014 |
20140266273 | TEST-YIELD IMPROVEMENT DEVICES FOR HIGH-DENSITY PROBING TECHNIQUES AND METHOD OF IMPLEMENTING THE SAME - A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head. | 09-18-2014 |
20140266281 | TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE - A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body. | 09-18-2014 |
20140354322 | PROBE CARD PARTITION SCHEME - A method of testing an integrated circuit die comprises partitioning a first probe card partition layout of the integrated circuit die having one or more sections comprising a first quantity of section types into a second probe card partition layout having a greater quantity of sections comprising a second quantity of section types, the second quantity of section types being less than the first quantity of section types. The method also comprises using one or more probe cards to test the sections in the second probe card partition layout, each of the one or more probe cards having a test contact pattern that corresponds with a test contact pattern of one of each section type included in the second probe card partition layout. | 12-04-2014 |