Patent application number | Description | Published |
20100025686 | SEMICONDUCTOR DEVICE WITH AMORPHOUS SILICON MONOS MEMORY CELL STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an oxide-nitride-oxide (ONO) charge trapping layer overlying the a-Si p-i-n diode junction and a metal control gate overlying the ONO layer. A method for making the a-Si MONOS memory cell structure is provided and can be repeated to expand the structure three-dimensionally. | 02-04-2010 |
20110045649 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH Al2O3/NANO-CRYSTALLINE Si LAYER - A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region. The method forms a sidewall structure overlying a side region of the polysilicon gate structure. | 02-24-2011 |
20110045661 | METHOD FOR MANUFACTURING NANO-CRYSTALLINE SILICON MATERIAL FOR SEMICONDUCTOR INTEGRATED CIRCUITS - A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. In a specific embodiment, the present invention includes providing a semiconductor substrate including a surface region. The method includes forming an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region according to a specific embodiment. The method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrsytalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers. | 02-24-2011 |
20110070711 | METHOD FOR MANUFACTURING NANO-CRYSTALLINE SILICON MATERIAL FROM CHLORIDE CHEMISTRIES FOR THE SEMICONDUCTOR INTEGRATED CIRCUITS - A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. The method includes providing a semiconductor substrate including a surface region. The method forms an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region. In a specific embodiment, the method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer using a chloro-silane species. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrsytalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers. | 03-24-2011 |
20110095396 | METHOD AND STRUCTURE FOR SILICON NANOCRYSTAL CAPACITOR DEVICES FOR INTEGRATED CIRCUITS - An improved semiconductor device, including a capacitor structure. The device has a first electrode member, which has a first length and a first width. The device also has a second electrode member, which has a second length and a second width. Additionally, the device includes a capacitor dielectric material provided between the first electrode member and the second electrode member according to a specific embodiment. Depending upon the embodiment, the capacitor dielectric material is made of a suitable material or materials such as Al | 04-28-2011 |
20110140190 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH ALUMINUM OXIDE LAYER - A method for manufacturing a twin bit cell structure with an aluminum oxide material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, an aluminum oxide material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The aluminum oxide material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed aluminum oxide material and the polysilicon gate structure. | 06-16-2011 |
20110140191 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH SILICON NITRIDE LAYER - A method for manufacturing a twin bit cell structure with a silicon nitride material includes forming a gate dielectric layer overlying a semiconductor substrate and a polysilicon gate structure overlying the gate dielectric layer. An undercut region is formed in each side of the gate dielectric layer underneath the polysilicon gate structure. Thereafter, an oxidation process is performed to form a first silicon oxide layer on a peripheral surface of the polysilicon gate structure and a second silicon oxide layer on an exposed surface of the semiconductor substrate. Then, a silicon nitride material is deposited over the first and second silicon oxide layers including the undercut region and the gate dielectric layer. The silicon nitride material is selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed silicon nitride material and the polysilicon gate structure. | 06-16-2011 |
20110140192 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH FLOATING POLYSILICON LAYER - A method for forming a twin-bit cell structure is provided. The method includes providing a semiconductor substrate including a surface region. A gate dielectric layer is formed overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer. In a specific embodiment, the method subjects the gate polysilicon structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the gate polysilicon structure. Preferably, an undercut region is allowed to be formed underneath the gate polysilicon structure. The method includes forming an undoped polysilicon material overlying the polysilicon gate structure including the undercut region and the gate dielectric layer. The undoped polysilicon material is subjected to a selective etching process to form an insert region in a portion of the undercut region while the insert region remains filled with the undoped polysilicon material. | 06-16-2011 |
20110156123 | METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH HAFNIUM OXIDE LAYER - A method for manufacturing a twin bit cell structure of with a hafnium oxide material includes providing a semiconductor substrate having a surface region and forming a gate dielectric layer overlying the surface region. The method forms a polysilicon gate structure overlying the gate dielectric layer and subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure. The method forms an undercut region underneath the polysilicon gate structure and subjects the polysilicon gate structure to an oxidization environment. Thereafter, the method forms a hafnium oxide material overlying the polysilicon gate structure including the undercut region and exposed portions of the gate dielectric layer. The hafnium oxide material is then selectively etched to form an insert region in a portion of the undercut region. A sidewall spacer is formed to isolate and protect the exposed hafnium oxide material. | 06-30-2011 |
20110204363 | AMORPHOUS SILICON MONOS OR MAS MEMORY CELL STRUCTURE WITH OTP FUNCTION - A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlying the substrate, and one or more source or drain regions embedded in the first dielectric layer with a co-planar surface of n-type a-Si and the first dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes a second dielectric layer on the a-Si p-i-n diode junction and a metal control gate overlying the second dielectric layer. Optionally the device with OTP function includes a conductive path formed between n-type a-Si layer and the metal control gate. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally. | 08-25-2011 |
20120091458 | SEMICONDUCTOR DEVICE WITH AMORPHOUS SILICON MAS MEMORY CELL STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally. | 04-19-2012 |
20120091462 | TFT MONOS OR SONOS MEMORY CELL STRUCTURES - A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. The dielectric layer is associated with a first surface. Each of the one or more source or drain regions includes an N | 04-19-2012 |
20130134485 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions. | 05-30-2013 |
20130134488 | Semiconductor Device and Manufacturing Method thereof - A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region. | 05-30-2013 |
20130168741 | COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR DEVICE AND ITS GATE-LAST FABRICATION METHOD - The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening. | 07-04-2013 |
20130248946 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region. | 09-26-2013 |
20130313619 | FIN FIELD-EFFECT-TRANSISTOR (FET) STRUCTURE AND MANUFACTURING METHOD - A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region, and doping top of the semiconductor substrate to form a doped layer at top surface of the semiconductor substrate over the first region and the second region. The method also includes etching the doped layer to form a first sub-fin in the first region and a first sub-fin in the second region, and forming an insulating layer over the semiconductor substrate including the first sub-fin in the first region and the first sub-fin in the second region. Further, the method includes removing top portions of the first sub-fin in the first region and the first sub-fin in the second region and forming corresponding second sub-fins. | 11-28-2013 |
20130334607 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a first region and an adjacent second region, and etching the semiconductor substrate to form a plurality of first trenches in the first region and a second trench in the second region. Fins are formed in between the adjacent first trenches. The width of the second trench is greater than the width of the first trench. The method also includes filling the first trenches with a first isolation material to form first insolation structures, and form sidewall spacers inside the second trench. Further, the method includes forming a third trench in the second trench by etching the exposed semiconductor substrate on the bottom of the second trench using the sidewall spacers as an etching mask, and filling the second trench and the third trench using a second isolation material to form a second isolation structure. | 12-19-2013 |
20140014968 | TRANSISTOR DEVICE AND FABRICATION METHOD - Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate. | 01-16-2014 |
20140110778 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a gate insulating layer formed on an inner wall of a substrate recess, a work function material layer formed on the gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, and a gate metal formed on the work function material layer. The method for manufacturing the semiconductor device includes forming a work function material layer on a gate insulating layer so as to apply a tensile stress or a compressive stress to a channel of a MOS field-effect transistor, wherein the gate insulating layer is formed on an inner wall of a substrate recess, and depositing a gate metal on the work function material layer. | 04-24-2014 |
20140203369 | FIN FIELD-EFFECT TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate, and forming a plurality of fins with hard mask layers and an isolation structure. The process also includes forming a first dummy gate layer on the fins and the isolation structure, and polishing the first dummy gate layer until the hard mask layer is exposed. Further, the method includes removing the hard mask layer to expose a top surface of the fins, and forming a second dummy gate material layer on the first dummy gate material layer. Further, the method also includes etching the second dummy gate layer and the first dummy gate layer to form a dummy gate on each of the fins. | 07-24-2014 |
20140239355 | FIN FIELD-EFFECT TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins. | 08-28-2014 |
20140319543 | FIN FIELD-EFFECT TRANSISTORS - A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins. | 10-30-2014 |
20150021669 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions. | 01-22-2015 |
20150037946 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device is provided. The method includes providing a fin protruding upwardly from or through a surface of a substrate, forming a to-be-sacrificed dummy gate enwrapping a first portion of the fin, forming a first insulating material layer so as to at least cover an exposed second portion of the fin, and selectively removing the dummy gate to thereby expose the first portion of the first semiconductor layer portion that was enwrapped by the dummy gate. The method further includes introducing, into the exposed portion of the first semiconductor layer portion, one or more dopants including a conductivity type reversing dopant, so as to form a channel region having a first conductivity type and at least two opposed channel control regions having a second conductivity type, wherein the channel control regions further comprise a portion formed above and adjoining a top of the channel region. | 02-05-2015 |