Patent application number | Description | Published |
20090065952 | Semiconductor Chip with Crack Stop - Various semiconductor chip crack stops and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor substrate that has a first corner defined by a first edge and a second edge. A crack stop is formed in the semiconductor substrate. The crack stop includes a first projection extending to the first edge and a second projection extending to the second edge to fence off a portion of the semiconductor substrate that includes the first corner. | 03-12-2009 |
20100207250 | Semiconductor Chip with Protective Scribe Structure - Apparatus and methods pertaining to die scribe structures are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating an active region of a semiconductor die so that the active region has at least one corner. A scribe structure is fabricated around the active region so that the scribe structure includes at least one fillet. | 08-19-2010 |
20110147916 | Semiconductor Chip Device with Solder Diffusion Protection - Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a first distance into the substrate. A barrier is formed in the first semiconductor chip that surrounds but is laterally separated from the first active circuitry portion and extends into the substrate a second distance greater than the first distance. | 06-23-2011 |
20120038061 | SEMICONDUCTOR CHIP WITH OFFSET PADS - A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures. | 02-16-2012 |
20120043539 | SEMICONDUCTOR CHIP WITH THERMAL INTERFACE TAPE - A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip. | 02-23-2012 |
20120043668 | STACKED SEMICONDUCTOR CHIPS WITH THERMAL MANAGEMENT - A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a first surface seated on the first semiconductor chip and a second surface adapted to thermally contact a heat spreader. The second surface includes a first aperture. A second semiconductor chip is placed in the first aperture. | 02-23-2012 |
20120043669 | STACKED SEMICONDUCTOR CHIP DEVICE WITH THERMAL MANAGEMENT CIRCUIT BOARD - A method of assembling a semiconductor chip device is provided that includes providing a circuit board including a surface with an aperture. A portion of a first heat spreader is positioned in the aperture. A stack is positioned on the first heat spreader. The stack includes a first semiconductor chip positioned on the first heat spreader and a substrate that has a first side coupled to the first semiconductor chip. | 02-23-2012 |
20120061821 | SEMICONDUCTOR CHIP WITH REDUNDANT THRU-SILICON-VIAS - A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias. | 03-15-2012 |
20120061852 | SEMICONDUCTOR CHIP DEVICE WITH POLYMERIC FILLER TRENCH - A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench. | 03-15-2012 |
20120061853 | SEMICONDUCTOR CHIP DEVICE WITH UNDERFILL - A method of manufacturing is provided that includes placing a removable cover on a surface of a substrate. The substrate includes a first semiconductor chip positioned on the surface. The first semiconductor chip includes a first sidewall. The removable cover includes a second sidewall positioned opposite the first sidewall. A first underfill is placed between the first semiconductor chip and the surface wherein the second sidewall provides a barrier to flow of the first underfill. Various apparatus are also disclosed. | 03-15-2012 |
20120074579 | SEMICONDUCTOR CHIP WITH REINFORCING THROUGH-SILICON-VIAS - A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side. | 03-29-2012 |
20120075807 | STACKED SEMICONDUCTOR CHIP DEVICE WITH THERMAL MANAGEMENT - A method of manufacturing is provided that includes placing a thermal management device in thermal contact with a first semiconductor chip of a semiconductor chip device. The semiconductor chip device includes a first substrate coupled to the first semiconductor chip. The first substrate has a first aperture. At least one of the first semiconductor chip and the thermal management device is at least partially positioned in the first aperture. | 03-29-2012 |
20120098119 | SEMICONDUCTOR CHIP DEVICE WITH LIQUID THERMAL INTERFACE MATERIAL - A method of manufacturing is provided that includes providing a semiconductor chip device that has a circuit board and a first semiconductor chip coupled thereto. A lid is placed on the circuit board. The lid includes an opening and an internal cavity. A liquid thermal interface material is placed in the internal cavity for thermal contact with the first semiconductor chip and the circuit board. | 04-26-2012 |
20120119767 | POWER CYCLING TEST ARRANGEMENT - A device instructs a power supply to provide a current to a power cycling test structure that includes a heat source interconnected with a package, via a first level interconnect mechanism, and a printed circuit board (PCB) interconnected with the package, via a second level interconnect mechanism. The device also monitors thermal feedback associated with the heat source, and monitors, based on the provided current, voltage feedback associated with the power cycling test structure. The device further determines a thermal profile of the power cycling test structure based on the thermal feedback and the voltage feedback. | 05-17-2012 |
20120241985 | SEMICONDUCTOR CHIP WITH SUPPORTIVE TERMINAL PAD - Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure. | 09-27-2012 |
20130049229 | SEMICONDUCTOR CHIP DEVICE WITH SOLDER DIFFUSION PROTECTION - Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip that has a substrate and a first active circuitry portion extending a first distance into the substrate. A barrier is formed in the first semiconductor chip that surrounds but is laterally separated from the first active circuitry portion and extends into the substrate a second distance greater than the first distance. | 02-28-2013 |
20130147028 | HEAT SPREADER FOR MULTIPLE CHIP SYSTEMS - Various heat spreaders and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a heat spreader that has a surface adapted to establish thermal contact with a first semiconductor chip and a second semiconductor chip on a substrate. The surface includes a first portion adapted to thermally contact a solder-based thermal interface material and a second portion having an opening adapted to hold an organic thermal interface material. | 06-13-2013 |
20130161814 | SEMICONDUCTOR CHIP WITH OFFSET PADS - A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures. | 06-27-2013 |
20130341783 | INTERPOSER WITH IDENTIFICATION SYSTEM - Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the identification information. | 12-26-2013 |
20130341802 | INTEGRATED CIRCUIT PACKAGE HAVING OFFSET VIAS - Integrated circuit packages comprise vias, each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the centre of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate. | 12-26-2013 |
20130342231 | SEMICONDUCTOR SUBSTRATE WITH ONBOARD TEST STRUCTURE - Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating a first test structure onboard an interposer that has a first side and second side opposite the first side. Additional test structures may be fabricated. | 12-26-2013 |
20140103506 | SEMICONDUCTOR CHIP DEVICE WITH POLYMERIC FILLER TRENCH - A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench. | 04-17-2014 |