Patent application number | Description | Published |
20080266778 | Memory module routing - In some embodiments a memory module circuit board includes a first surface adapted to couple a first plurality of memory devices, a plurality of signal lines, and a command and address bus coupled to the signal lines. The command and address bus is routed from the signal lines and adapted to couple to at least one of the first plurality of memory devices in a manner that does not require the command and address bus lines to turn more than approximately ninety degrees before coupling to the at least one of the first plurality of memory devices. Other embodiments are described and claimed. | 10-30-2008 |
20100080132 | DYNAMIC CONFIGURATION OF POTENTIAL LINKS BETWEEN PROCESSING ELEMENTS - According to some embodiments, first and second processing elements may be provided on a die, and there may be a plurality of potential communication links between the first and second processing elements. Moreover, control logic may be provided on the die to dynamically activate at least some of the potential communication links (e.g., based on a current bandwidth appropriate between the first and second processing elements). | 04-01-2010 |
20100191920 | Providing Address Range Coherency Capability To A Device - In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed. | 07-29-2010 |
20120199973 | INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT - A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed. | 08-09-2012 |
20130341790 | INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT - A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed. | 12-26-2013 |
20140181348 | CROSSTALK AWARE DECODING FOR A DATA BUS - Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream. | 06-26-2014 |
20140181357 | CROSSTALK AWARE ENCODING FOR A DATA BUS - Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a plurality of digital inputs. The signaling module is to encode data received at the plurality of digital inputs to generate encoded data. Based on the encoded data, the signaling module can drive line voltages on a plurality of signal lines of a bus. Each one of the plurality of line voltages corresponds to a weighted sum of the data received at the plurality of digital inputs. | 06-26-2014 |
20150269109 | METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRANSACTION LAYER PACKETS - Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express™ (PCIe™) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe™ format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips. | 09-24-2015 |