Patent application number | Description | Published |
20080240110 | MEMORY SYSTEM WITH APPARATUS AND METHOD TO ENABLE BALANCED BANDWIDTH UTILIZATION - A memory subsystem includes Data Store | 10-02-2008 |
20100153647 | Cache-To-Cache Cast-In - A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache. | 06-17-2010 |
20100235576 | Handling Castout Cache Lines In A Victim Cache - A victim cache memory includes a cache array, a cache directory of contents of the cache array, and a cache controller that controls operation of the victim cache memory. The cache controller, responsive to receiving a castout command identifying a victim cache line castout from another cache memory, causes the victim cache line to be held in the cache array. If the other cache memory is a higher level cache in the cache hierarchy of the processor core, the cache controller marks the victim cache line in the cache directory so that it is less likely to be evicted by a replacement policy of the victim cache, and otherwise, marks the victim cache line in the cache directory so that it is more likely to be evicted by the replacement policy of the victim cache. | 09-16-2010 |
20100235577 | VICTIM CACHE LATERAL CASTOUT TARGETING - A data processing system includes a plurality of processing units coupled by an interconnect fabric. In response to a data request, a victim cache line is selected for castout from a first lower level cache of a first processing unit, and a target lower level cache of one of the plurality of processing units is selected based upon architectural proximity of the target lower level cache to a home system memory to which the address of the victim cache line is assigned. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that the target lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache. | 09-16-2010 |
20100235584 | Lateral Castout (LCO) Of Victim Cache Line In Data-Invalid State - A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect fabric a lateral castout (LCO) command identifying the victim cache line to be castout from the first lower level cache, indicating the data-invalid coherence state, and indicating that a lower level cache is an intended destination of the victim cache line. In response to a coherence response to the LCO command indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in a second lower level cache of a second processing unit in the data-invalid coherence state. | 09-16-2010 |
20110047352 | MEMORY COHERENCE DIRECTORY SUPPORTING REMOTELY SOURCED REQUESTS OF NODAL SCOPE - A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node. | 02-24-2011 |
20120203976 | MEMORY COHERENCE DIRECTORY SUPPORTING REMOTELY SOURCED REQUESTS OF NODAL SCOPE - A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node. | 08-09-2012 |
20140149681 | COHERENT PROXY FOR ATTACHED PROCESSOR - A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request from an attached processor (AP) and an expected coherence state of a target address of the memory access request with respect to a cache memory of the AP. In response, the CAPP determines a coherence state of the target address and whether or not the expected state matches the determined coherence state. In response to determining that the expected state matches the determined coherence state, the CAPP issues a memory access request corresponding to that received from the AP on a system fabric of the primary coherent system. In response to determining that the expected state does not match the coherence state determined by the CAPP, the CAPP transmits a failure message to the AP without issuing on the system fabric a memory access request corresponding to that received from the AP. | 05-29-2014 |
20140149682 | PROGRAMMABLE COHERENT PROXY FOR ATTACHED PROCESSOR - A coherent attached processor proxy (CAPP) within a primary coherent system participates in an operation on a system fabric of the primary coherent system on behalf of an attached processor (AP) that is external to the primary coherent system and that is coupled to the CAPP. The operation includes multiple components communicated with the CAPP including a request and at least one coherence message. The CAPP determines one or more of the components of the operation by reference to at least one programmable data structure within the CAPP that can be reprogrammed. | 05-29-2014 |
20140149683 | PROGRAMMABLE COHERENT PROXY FOR ATTACHED PROCESSOR - A coherent attached processor proxy (CAPP) within a primary coherent system participates in an operation on a system fabric of the primary coherent system on behalf of an attached processor (AP) that is external to the primary coherent system and that is coupled to the CAPP. The operation includes multiple components communicated with the CAPP including a request and at least one coherence message. The CAPP determines one or more of the components of the operation by reference to at least one programmable data structure within the CAPP that can be reprogrammed. | 05-29-2014 |
20140149686 | COHERENT ATTACHED PROCESSOR PROXY SUPPORTING MASTER PARKING - In response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from the AP. | 05-29-2014 |
20140149688 | COHERENT ATTACHED PROCESSOR PROXY SUPPORTING MASTER PARKING - In response to receiving a memory access request and expected coherence state at an attached processor at a coherent attached processor proxy (CAPP), the CAPP determines that a conflicting request is being serviced. In response to determining that the CAPP is servicing a conflicting request and that the expected state matches, a master machine of the CAPP is allocated in a Parked state to service the memory access request after completion of service of the conflicting request. The Parked state prevents servicing by the CAPP of a further conflicting request snooped on the system fabric. In response to completion of service of the conflicting request, the master machine transitions out of the Parked state and issues on the system fabric a memory access request corresponding to that received from the AP. | 05-29-2014 |
20140149689 | COHERENT PROXY FOR ATTACHED PROCESSOR - A coherent attached processor proxy (CAPP) of a primary coherent system receives a memory access request from an attached processor (AP) and an expected coherence state of a target address of the memory access request with respect to a cache memory of the AP. In response, the CAPP determines a coherence state of the target address and whether or not the expected state matches the determined coherence state. In response to determining that the expected state matches the determined coherence state, the CAPP issues a memory access request corresponding to that received from the AP on a system fabric of the primary coherent system. In response to determining that the expected state does not match the coherence state determined by the CAPP, the CAPP transmits a failure message to the AP without issuing on the system fabric a memory access request corresponding to that received from the AP. | 05-29-2014 |
20140201460 | DATA RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor. | 07-17-2014 |
20140201464 | EPOCH-BASED RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP includes an epoch timer that advances at regular intervals to define epochs of operation of the CAPP. Each of one or more entries in a data structure in the CAPP are associated with a respective epoch. Recovery operations for the CAPP are initiated based on a comparison of an epoch indicated by the epoch timer and the epoch associated with one of the one or more entries in the data structure. | 07-17-2014 |
20140201465 | ACCELERATED RECOVERY FOR SNOOPED ADDRESSES IN A COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order. | 07-17-2014 |
20140201466 | DATA RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor. | 07-17-2014 |
20140201467 | EPOCH-BASED RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP includes an epoch timer that advances at regular intervals to define epochs of operation of the CAPP. Each of one or more entries in a data structure in the CAPP are associated with a respective epoch. Recovery operations for the CAPP are initiated based on a comparison of an epoch indicated by the epoch timer and the epoch associated with one of the one or more entries in the data structure. | 07-17-2014 |
20140201468 | ACCELERATED RECOVERY FOR SNOOPED ADDRESSES IN A COHERENT ATTACHED PROCESSOR PROXY - A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order. | 07-17-2014 |
20140250275 | SELECTION OF POST-REQUEST ACTION BASED ON COMBINED RESPONSE AND INPUT FROM THE REQUEST SOURCE - A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions. | 09-04-2014 |
20140250276 | SELECTION OF POST-REQUEST ACTION BASED ON COMBINED RESPONSE AND INPUT FROM THE REQUEST SOURCE - A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions. | 09-04-2014 |
20140365733 | INTEGRATED CIRCUIT SYSTEM HAVING DECOUPLED LOGICAL AND PHYSICAL INTERFACES - An integrated circuit system including a first integrated circuit chip including first logic, a second integrated circuit chip, and second logic distributed across the first and second integrated circuit chips. The second logic includes a first unit integrated in the first integrated circuit chip and a second unit integrated in the second integrated circuit chip. The integrated circuit system further includes a physical communication link coupling the first unit in the first integrated circuit chip and the second unit in the second integrated circuit chip and a request interface between the first logic and first unit of the second logic. The request interface is implemented in the first integrated circuit such that communication via the request interface between the first logic and the first unit of the second logic has low latency and such that the request interface is decoupled from the physical communication link. | 12-11-2014 |
20140379989 | COHERENT ATTACHED PROCESSOR PROXY HAVING HYBRID DIRECTORY - A coherent attached processor proxy (CAPP) includes transport logic having a first interface configured to support communication with a system fabric of a primary coherent system and a second interface configured to support communication with an attached processor (AP) that is external to the primary coherent system and that includes a cache memory that holds copies of memory blocks belonging to a coherent address space of the primary coherent system. The CAPP further includes one or more master machines that initiate memory access requests on the system fabric of the primary coherent system on behalf of the AP, one or more snoop machines that service requests snooped on the system fabric, and a CAPP directory having a precise directory having a plurality of entries each associated with a smaller data granule and a coarse directory having a plurality of entries each associated with a larger data granule. | 12-25-2014 |
20140379997 | COHERENT ATTACHED PROCESSOR PROXY HAVING HYBRID DIRECTORY - A coherent attached processor proxy (CAPP) includes transport logic having a first interface configured to support communication with a system fabric of a primary coherent system and a second interface configured to support communication with an attached processor (AP) that is external to the primary coherent system and that includes a cache memory that holds copies of memory blocks belonging to a coherent address space of the primary coherent system. The CAPP further includes one or more master machines that initiate memory access requests on the system fabric of the primary coherent system on behalf of the AP, one or more snoop machines that service requests snooped on the system fabric, and a CAPP directory having a precise directory having a plurality of entries each associated with a smaller data granule and a coarse directory having a plurality of entries each associated with a larger data granule. | 12-25-2014 |