Patent application number | Description | Published |
20080224178 | RESISTIVE MEMORY AND METHOD - A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area. | 09-18-2008 |
20080259676 | Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Computer Program Product - According to one embodiment of the present invention, an integrated circuit is provided which includes a plurality of resistivity changing cells. At least two resistance ranges are assigned to each resistivity changing cell, each resistance range defining a possible state of the resistivity changing cell. The integrated circuit is operable in a cell initializing mode in which initializing signals are applied to the resistivity changing cells. The strengths and durations of the initializing signals are chosen such that the resistance of each resistivity changing cell is shifted into one of the resistance ranges assigned to the resistivity changing cell. | 10-23-2008 |
20080263415 | Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Fabricating an Integrated Circuit, Computer Program Product, and Computing System - According to one embodiment of the present invention, an integrated circuit includes a plurality of memory cells, the integrated circuit being operable in a memory cell testing mode in which testing signals are applied to the memory cells, wherein the strengths and durations of the testing signals at least partly differ from the strengths and durations of programming signals or sensing signals used for programming and sensing memory states of the memory cells. | 10-23-2008 |
20090028213 | Temperature Sensor, Integrated Circuit, Memory Module, and Method of Collecting Temperature Treatment Data - According to one embodiment of the present invention, a temperature sensor is provided, including a first electrode, a second electrode, a nanoporous material disposed between the first electrode and the second electrode, and a diffusion material which is located outside the nanoporous material that is capable of diffusion into the nanoporous material. The amount of diffusion material diffusing into the nanoporous material is dependent on the temperature to which the temperature sensor is exposed. The resistance of the nanoporous material is dependent on the amount of diffusion material diffusing into the nanoporous material. | 01-29-2009 |
20090073743 | Method of Manufacturing a Memory Cell, Memory Cell, Integrated Circuit, and Memory Module - A method of fabricating a memory cell including a solid electrolyte layer doped with metallic material and an electrode layer arranged above the solid electrolyte layer. The method includes doping a solid electrolyte layer with metallic material and forming an electrode layer above the solid electrolyte layer, wherein doping the solid electrolyte layer is carried out before forming the electrode layer. | 03-19-2009 |
20090103350 | Method of Testing an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Integrated Circuit - According to one embodiment of the present invention, a method of testing a memory device including a memory cell array is provided, the method including: dividing the memory cell array into a plurality of memory cell array subunits, each memory cell array subunit including a plurality of resistivity changing memory cells; simultaneously testing all resistivity changing memory cells of a memory cell array subunit using a common testing signal; and repeating the testing for all further memory cell array subunits. | 04-23-2009 |
20100058018 | Memory Scheduler for Managing Internal Memory Operations - An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller. | 03-04-2010 |
20100084741 | Integrated Circuit - According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element. | 04-08-2010 |
20120026781 | RESISTIVE MEMORY AND METHOD - A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area. | 02-02-2012 |