Patent application number | Description | Published |
20090121737 | CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY - An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified. | 05-14-2009 |
20110121438 | EXTENDED UNDER-BUMP METAL LAYER FOR BLOCKING ALPHA PARTICLES IN A SEMICONDUCTOR DEVICE - An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. | 05-26-2011 |
20110191729 | Method and Apparatus for Interconnect Layout in an Integrated Circuit - An embodiment of the invention relates to a computer-implemented method of designing an integrated circuit (IC). In this embodiment, layout data describing conductive layers of the integrated circuit on a substrate is generated according to design specification data for the integrated circuit. The conductive layers include a topmost layer of bond pads. Metal structures in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers within a threshold volume under each of the bond pads. A description of the layout data is generated on one or more masks for manufacturing the integrated circuit. By maximizing metal density in the superimposed plane, vertical channels through the dielectric material in the interconnect are reduced or eliminated. Thus, alpha particles cannot readily penetrate the interconnect and reach the underlying semiconductor substrate, reducing soft errors, such as single event upsets in memory cells. | 08-04-2011 |
20110210443 | SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION AND METHOD OF FORMING SAME - An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated. | 09-01-2011 |
20120199959 | EXTENDED UNDER-BUMP METAL LAYER FOR BLOCKING ALPHA PARTICLES IN A SEMICONDUCTOR DEVICE - An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. A UBM layer is disposed between the solder bump and the semiconductor portion and includes the UBM pad and a UBM field. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to block alpha particles emitted from the surface of the solder bump from causing an upset event in the semiconductor portion. The UBM field is separated from each UBM pad by a gap extending from the UBM pad to the UBM field so as to electrically isolate the UBM field from the UBM pad. | 08-09-2012 |
20140048887 | INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY - An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described. | 02-20-2014 |
20140145293 | INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY - An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors. | 05-29-2014 |
20140205934 | SINGLE RETICLE APPROACH FOR MULTIPLE PATTERNING TECHNOLOGY - A reticle for multiple patterning a layer of an integrated circuit die includes a first portion with a first layout pattern for multiple patterning the layer of the integrated circuit die, and a second portion with a second layout pattern for multiple patterning the layer of the integrated circuit die. The first layout pattern is different from the second layout pattern. | 07-24-2014 |
20150069577 | REMOVAL OF ELECTROSTATIC CHARGES FROM INTERPOSER FOR DIE ATTACHMENT - A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network. | 03-12-2015 |