| Patent application number | Description | Published |
|---|
| 20080229085 | Switching Drivers Between Processors - Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode. | 09-18-2008 |
| 20080232174 | Interleaving Charge Pumps for Programmable Memories - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 09-25-2008 |
| 20080270678 | COMMAND RESEQUENCING IN MEMORY OPERATIONS - Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution. | 10-30-2008 |
| 20080288712 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 11-20-2008 |
| 20090147570 | USE OF 8-BIT OR HIGHER A/D FOR NAND CELL VALUE - A system and method, including computer software, for storing digital information uses multiple NAND flash memory cells. Each memory cell is adapted to receive charge during a write operation to an analog voltage that corresponds to a data value having a binary representation of more than 4 bits. An analog-to-digital converter converts the analog voltage from each memory cell into a digital representation of the analog voltage during a read operation of each cell. | 06-11-2009 |
| 20090172481 | Partial Voltage Read of Memory - A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital values representing partial voltage levels are checked for errors (e.g., by an error correction code (ECC) engine). If the values can be corrected, then the values are released for host access. If the values cannot be corrected, then a full voltage read is performed on the memory cells after the voltage levels have substantially settled. Digital values corresponding to the full voltage reads can be released for host access. The use of partial voltage reads results in faster read of solid state memory devices. | 07-02-2009 |
| 20090237994 | Iterative Memory Cell Charging Based on Reference Cell Value - Systems and methods, including computer software for writing to a memory device include applying charge to each of multiple memory cells for storage of a selected data value in each memory cell. The memory cells include a first reference memory cell, and each data value is selected from a group of possible data values. Each possible data value has a corresponding target voltage level, and the first reference memory cell has a corresponding predetermined first reference target voltage level. The voltage level in the first reference memory cell is detected. A determination is made whether the voltage level in the first reference memory cell is less than the first reference target voltage level. Additional charge is applied to the memory cells upon the determination that the voltage level in the first reference memory cell is less than the first reference target voltage. | 09-24-2009 |
| 20090285037 | INTERLEAVING CHARGE PUMPS FOR PROGRAMMABLE MEMORIES - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 11-19-2009 |
| 20090285038 | INTERLEAVING CHARGE PUMPS FOR PROGRAMMABLE MEMORIES - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 11-19-2009 |
| 20090323418 | Use of Alternative Value in Cell Detection - A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values. | 12-31-2009 |
| 20100002512 | DISABLING FAULTY FLASH MEMORY DIES - Articles and associated methods and systems relate to disabling defective flash memory dies in a device containing multiple flash memory dies. Packages containing multiple flash memory dies may be labeled to indicate a flash memory data storage capacity based on the flash memory dies that are not disabled. Various disabling methods may be applied at the die level, package level, and/or board level. | 01-07-2010 |
| 20100020604 | SHIFTING REFERENCE VALUES TO ACCOUNT FOR VOLTAGE SAG - A system and method, including software implemented techniques, can be used to adjust for sag in stored data values. Charge is applied to multiple memory cells, and each memory cell is charged to a target voltage corresponding to a data value. The memory cells include a reference cell that is charged to a predetermined voltage. A voltage level in the reference cell is detected, and voltage levels from a group of memory cells are also detected. An adjustment is performed based upon the difference between the detected voltage level in the reference cell and the predetermined voltage. | 01-28-2010 |
| 20100070798 | Maintenance Operations for Multi-Level Data Storage Cells - Systems and methods, including computer software, for reading data from a flash memory cell involve detecting voltages from a group of memory cells. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from a plurality of possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined. A combination of alternative data values is selected, and an error detection test is performed using the metadata associated with the memory cells and the selected combination of alternative data values. | 03-18-2010 |
| 20100070799 | DYNAMIC CELL BIT RESOLUTION - A system and method, including computer software, is used to write to a flash memory device that includes multiple memory cells. One or more of the memory cells are written at a first resolution corresponding to a first number of bits of data. A signal to write at a second resolution corresponding to a second number of bits of data is received. One or more of the memory cells are written at the second resolution. | 03-18-2010 |
| 20100070801 | MAINTENANCE OPERATIONS FOR MULTI-LEVEL DATA STORAGE CELLS - Systems and methods, including computer software, for reading data from a flash memory cell involve detecting voltages from a group of memory cells. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from a plurality of possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined. A combination of alternative data values is selected, and an error detection test is performed using the metadata associated with the memory cells and the selected combination of alternative data values. | 03-18-2010 |
| 20100157674 | Two Levels of Voltage Regulation Supplied for Logic and Data Programming Voltage of a Memory Device - Systems and methods involve the use of a flash memory device having multiple flash memory cells. A first interface is adapted to receive power for selectively programming each flash memory cell. A second interface is adapted to receive power supplied to logic level circuitry to perform the selection of flash memory cells to be supplied with power from the first input during a write operation. | 06-24-2010 |
| 20100162012 | REPORTING FLASH MEMORY OPERATING VOLTAGES - Apparatus and associated systems, methods and computer program products relate to using information stored in a flash memory to adjust the operating voltage supplied to the flash memory. The voltage information indicates a minimum operating voltage at which to operate the flash memory device. In general, operating a flash memory device near a minimal operating voltage may substantially minimize power consumption. The minimum operating voltage for individual flash memory devices may vary from IC to IC, by manufacturing lot, and by manufacturer. In a product, the minimum operating voltage for a particular flash memory may be determined, for example, by a controller built-in to a flash memory reporting (automatically or in response to a query) the minimum operating voltage (e.g., 2.5 V, 3.15 V) to a memory controller or microprocessor. The stored voltage information may further include information to adjust the operating voltage based on temperature. | 06-24-2010 |
| 20100228909 | Caching Performance Optimization - A method for managing data storage is described. The method includes receiving data from an external host at a peripheral storage device, detecting a file system type of the external host, and adapting a caching policy for transmitting the data to a memory accessible by the storage device, wherein the caching policy is based on the detected file system type. The detection of the file system type can be based on the received data. The detection bases can include a size of the received data. In some implementations, the detection of the file system type can be based on accessing the memory for file system type indicators that are associated with a unique file system type. Adapting the caching policy can reduce a number of data transmissions to the memory. The detected file system type can be a file allocation table (FAT) system type. | 09-09-2010 |
| 20100332741 | Interleaving Policies for Flash Memory - Articles and associated methods and systems relate to selecting read interleaving policies independently of selecting write interleaving policies. In various implementations, the selection may be static or dynamic during operation. In implementations that dynamically select read interleaving policies and write interleaving policies, the selection may be based on various operating conditions, such as temperature, power source, battery voltage, and operating mode. Examples of operating modes may include (1) reading or writing to flash memory when connected to an external power source, (2) reading from flash memory when powered by portable power source (e.g., battery), and (3) writing to flash memory when powered by a portable power source. | 12-30-2010 |
| 20110015778 | DATA CARTRIDGE AND TAPE LIBRARY INCLUDING FLASH MEMORY - A data storage system for use with a plurality of tape cartridges is provided. Each tape cartridge includes a length of tape media and an amount of flash memory. The data storage system includes a tape cartridge library having a plurality of storage cells. Each storage cell is configured to store a tape cartridge. The tape cartridge library further includes a plurality of tape drives. Each tape drive is configured to access a tape cartridge when the tape cartridge is received in the tape drive. The system further includes a robotic tape mover and a flash memory access mechanism. The robotic tape mover moves tape cartridges between the plurality of storage cells and the plurality of tape drives. The flash memory access mechanism is configured in the tape cartridge library to access the flash memory of a tape cartridge when the tape cartridge is in the tape cartridge library. | 01-20-2011 |
| 20110029725 | Switching Drivers Between Processors - Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode. | 02-03-2011 |
| 20110154163 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 06-23-2011 |
