| Patent application number | Description | Published |
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| 20080222587 | Integrated Circuit Cell Library for Multiple Patterning - A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium. | 09-11-2008 |
| 20090023101 | LITHOGRAPHY TRACK SYSTEMS AND METHODS FOR ELECTRONIC DEVICE MANUFACTURING - The present invention provides systems, methods, and apparatus for processing a lot of substrates in a lithography track system with an integrate metrology sensor. The invention includes performing a coating process on substrates; transferring the substrates to a stepper for alignment and exposure; transferring the substrates to a post-exposure bake chamber for bake; and performing metrology on the substrates in the lithography track system. The invention may further include automatically reworking substrates in an integrated rework chamber within the lithography track system. Numerous other aspects are provided. | 01-22-2009 |
| 20090023230 | METHODS AND APPARATUS FOR DEPOSITING AN ANTI-REFLECTION COATING - Systems, methods, and apparatus are provided for depositing an anti-reflection film on a substrate. A substrate is transported to a metrology tool. A characteristic of the substrate is measured, via the metrology tool. A recipe for an anti-reflection film is determined, based on the measured characteristic. The substrate is transported from the metrology tool to a process chamber. The recipe is employed to form an anti-reflection film on the substrate within the process chamber. Numerous other aspects are provided. | 01-22-2009 |
| 20090032898 | Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same - A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo. | 02-05-2009 |
| 20090032967 | Semiconductor Device with Dynamic Array Section - A semiconductor chip is provided to include one or more distinct but functionally interfaced dynamic array sections. Each dynamic array section follows a dynamic array architecture that requires conductive features to be linearly defined along a virtual grate in each of a plurality of levels of the semiconductor chip. Each virtual grate is perpendicular to another virtual grate that is either a level above or a level below. Each virtual grate is defined by a framework of parallel lines spaced at a constant pitch. Some of the lines in the virtual grate are occupied by multiple conductive features. A substantially uniform gap can be maintained between proximate ends of adjacent conductive features that occupy a common line in the virtual grate. The substantially uniform gap between the proximate ends of adjacent conductive features can be maintained within each line in the virtual grate that is occupied by multiple conductive features. | 02-05-2009 |
| 20090037864 | Methods for Designing Semiconductor Device with Dynamic Array Section - A method is provided for designing a semiconductor chip having one or more functionally interfaced dynamic array sections. A virtual grate is laid out for conductive features used to define a gate electrode level of a dynamic array section. The virtual grate is defined by a framework of parallel lines defined at a substantially constant pitch. One or more conductive features are arranged along every line of the virtual grate. For each line of the virtual grate, a gap is defined between proximate ends of each pair of adjacent conductive features which are arranged along a common line of the virtual grate. Each gap is defined to maintain a substantially consistent separation between proximate ends of conductive features. Each conductive feature is defined to be devoid of a substantial change in direction, such that the conductive features remain substantially aligned to the framework of parallel lines of the virtual grate. | 02-05-2009 |
| 20090066358 | METHODS AND APPARATUS FOR DETECTING DEFECTS IN INTERCONNECT STRUCTURES - In some aspects, a method is provided for detecting a void in a test structure that comprises (a) measuring a resistance of the test structure; (b) applying a stress to the test structure at increasing levels until at least one of: (i) the measured resistance of the test structure exceeds a predetermined resistance threshold; and (ii) the stress level reaches a predetermined stress maximum; (c) detecting a void if the measured resistance of the test structure exceeds the predetermined resistance threshold; and (d) determining that the test structure is void free if the stress level reaches the predetermined stress maximum without the measured resistance of the test structure exceeding the predetermined resistance threshold. Numerous other aspects are provided. | 03-12-2009 |
| 20090100396 | Methods and Systems for Process Compensation Technique Acceleration - Selected cells in a semiconductor chip layout are replaced with corresponding PCT pre-processed cells. Each PCT pre-processed cell represents a particular selected cell having been previously subjected to a cell-level-PCT-processing operation so as to include PCT-based cell layout adjustments. Following replacement of the selected cells in the semiconductor chip layout with corresponding PCT pre-processed cells, a chip-wide PCT processing operation is performed on the semiconductor chip layout for a given chip level. The presence of the PCT pre-processed cells in the semiconductor chip layout serves to accelerate the chip-wide PCT processing of the semiconductor chip layout. The chip-wide PCT processed semiconductor layout for the given chip level is recorded on a persistent storage medium. | 04-16-2009 |
| 20090108360 | METHODS, STRUCTURES AND DESIGNS FOR SELF-ALIGNING LOCAL INTERCONNECTS USED IN INTEGRATED CIRCUITS - Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions. The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers. The method also includes designing a local interconnect layer between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates. | 04-30-2009 |
| 20090127636 | Diffusion Variability Control and Transistor Device Sizing Using Threshold Voltage Implant - A transistor is defined to include a substrate portion and a diffusion region defined in the substrate portion so as to provide an operable transistor threshold voltage. An implant region is defined within a portion of the diffusion region so as to transform the operable transistor threshold voltage of the diffusion region portion into an inoperably high transistor threshold voltage. A gate electrode is defined to extend over both the diffusion region and the implant region. A first portion of the gate electrode defined over the diffusion region forms a first transistor segment having the operable transistor threshold voltage. A second portion of the gate electrode defined over the implant region forms a second transistor segment having the inoperably high transistor threshold voltage. Therefore, a boundary of the implant region defines a boundary of the operable first transistor segment. | 05-21-2009 |
| 20090152734 | Super-Self-Aligned Contacts and Method for Making the Same - A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact. | 06-18-2009 |
| 20090294981 | Methods for Defining and Using Co-Optimized Nanopatterns for Integrated Circuit Design and Apparatus Implementing Same - A set of layout nanopatterns is defined. Each layout nanopattern is defined by relative placements of a particular type of layout feature within a lithographic window of influence. A design space is defined as a set of layout parameters and corresponding value ranges that affect manufacturability of a layout. Layouts are created for the set of layout nanopatterns such that the created layouts cover the design space. The layouts for the set of layout nanopatterns are then optimized for manufacturability. A point in the design space is selected where the set of layout nanopatterns are co-optimized for manufacturability. A circuit layout is created based on the selected point in design space using the corresponding set of co-optimized layout nanopatterns. The optimized layouts for the set of layout nanopatterns and the associated circuit layout can be recorded in a digital format on a computer readable storage medium. | 12-03-2009 |
| 20100031211 | Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and Fabrication - Problematic open areas are identified in a semiconductor wafer layout. The problematic open areas have a size variation relative to one or more neighboring open areas of the layout sufficient to cause adverse microloading variation. In one embodiment, the adverse microloading variation is controlled by shifting a number of layout features to interdict the problematic open areas. In another embodiment, the adverse microloading variation is controlled by defining and placing a number of dummy layout features to shield actual layout features that neighbor the problematic open areas. In another embodiment, the adverse microloading variation is controlled by utilizing sacrificial layout features which are actually fabricated on the wafer temporarily to eliminate microloading variation, and which are subsequently removed from the wafer to leave behind the desired permanent structures. | 02-04-2010 |
| 20100306719 | Integrated Circuit Cell Library with Cell-Level Process Compensation Technique (PCT) Application and Associated Methods - A layout of cells is generated to satisfy a netlist of an integrated circuit. Cell-level process compensation technique (PCT) processing is performed on a number of levels of one or more cells in the layout to generate a PCT processed version of the one more cells in the layout. An as-fabricated aerial image of each PCT processed cell level is generated to facilitate evaluation of PCT processing adequacy. Cell-level circuit extraction is performed on the PCT processed version of each cell using the generated as-fabricated aerial images. The cell-level PCT processing and cell-level circuit extraction are performed before placing and routing of the layout on a chip. The PCT processed version of the one or more cells and corresponding as-fabricated aerial images are stored in a cell library. | 12-02-2010 |
| 20110108890 | Semiconductor Device with Dynamic Array Sections Defined and Placed According to Manufacturing Assurance Halos - An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending perpendicular to the first direction. Some of the three or more linear conductive segments within the gate electrode levels of the adjoining pair of dynamic array sections are co-aligned in the first direction and separated by an end-to-end spacing that spans the co-located portions of outer peripheral boundary segments of the adjoining pair of dynamic array sections. Each of these end-to-end spacings is sized to ensure that each gate electrode level manufacturing assurance halo portion of the first adjoining pair of dynamic array sections is devoid of the co-aligned linear conductive segments. | 05-12-2011 |
| 20110108891 | Semiconductor Device with Dynamic Array Sections Defined and Placed According to Manufacturing Assurance Halos - An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending in the first direction. At least one of the linear conductive segments within the gate electrode level of a given dynamic array section is a non-gate linear conductive segment that does not form a gate electrode of a transistor. The non-gate linear conductive segment of either of the adjoining pair of dynamic array sections spans the co-located portion of outer peripheral boundary segment toward the other of the adjoining pair of dynamic array sections, and is contained within gate electrode level manufacturing assurance halo portions of the adjoining pair of dynamic array sections. | 05-12-2011 |
| 20110161909 | Methods for Designing Semiconductor Device with Dynamic Array Section - A method is provided for designing an integrated circuit device. The method includes placing four transistors of a first transistor type and four transistors of a second transistor type within a gate electrode level. Each of the transistors includes a respective linear-shaped gate electrode segment positioned to extend lengthwise in a first direction. The transistors of the first and second transistor types are placed according to a substantially equal centerline-to-centerline spacing as measured perpendicular to the first direction. A first linear conductive segment is placed to electrically connect the gate electrodes of the first transistors of the first and second transistor types. A second linear conductive segment is placed to electrically connect the gate electrodes of the fourth transistors of the first and second transistor types. A third linear conductive segment is placed beside either the first or second linear conductive segment. | 06-30-2011 |
