| Patent application number | Description | Published |
|---|
| 20080250092 | SYSTEM FOR CONVOLUTION CALCULATION WITH MULTIPLE COMPUTER PROCESSORS - A system for calculating a convolution of a data function with a filter function utilizing an array of processors including first and last processors. A coefficient value based on a derivation of the filter function and a data value representative of the data function are multiplied to produce a current intermediate value. Except in the first processor, a prior intermediate value is then added to the current intermediate value. Except in the last processor, the data and current intermediate values are then sent to the next processor. Then the last processor's prior intermediate value, if any, is added to its current intermediate value to produce a result value, wherein the result values collectively are representative of the convolution of the data function with the filter function. | 10-09-2008 |
| 20080263118 | System for convolution calculation with multiple computer processors - A process for loading a signal data values and convolution filter coefficient values into a target processor (c | 10-23-2008 |
| 20080270751 | SYSTEM AND METHOD FOR PROCESSING DATA IN A PIPELINE OF COMPUTERS - A series of computers to process data including a first and a last computer. Each of the computers except the first is preceded by a prior computer and each except the last is followed by a subsequent computer. A logic reads new data via a first data path and a logic writes old data via a second data path. A logic process the new data to produce the old data and, except for the last computer, a storage element stores the old data. The logic to write operates after the logic to read and the logic to write operates before the logic to process. | 10-30-2008 |
| 20080282062 | Method and apparatus for loading data and instructions into a computer - A computer array ( | 11-13-2008 |
| 20090033536 | Method and Apparatus for Digital to Analog Conversion - The apparatus described is a multi-core processor | 02-05-2009 |
| 20090083350 | Shift-add based random number generation - A system for pseudorandom number generation. A processor is provided that has a first memory to hold a first value and a second memory to hold a second value. Then a logic performs a +* operation while a looping condition is true. | 03-26-2009 |
| 20090300334 | Method and Apparatus for Loading Data and Instructions Into a Computer - A computer array ( | 12-03-2009 |
| 20090319755 | Method and Apparatus for High Speed Data Stream Splitter on an Array of Processors - A method and apparatus for processing a stream of data. The apparatus includes an array of processors connected to one another by single drop busses. The data stream is inputed to one of the processors | 12-24-2009 |
