| Patent application number | Description | Published |
|---|
| 20110279153 | HIGH-PRECISION OSCILLATOR SYSTEMS WITH FEED FORWARD COMPENSATION FOR CCFL DRIVER SYSTEMS AND METHODS THEREOF - System and method for generating one or more ramp signals. The method includes an oscillator configured to generate at least a clock signal, and a ramp signal generator configured to receive at least the clock signal and generate a first ramp signal. Additionally, the ramp signal generator is coupled to a first resistor including a first terminal and a second terminal. The first resistor is configured to receive an input voltage at the first terminal and is coupled to the ramp signal generator at the second terminal. Moreover, the first resistor is associated with a first resistance value. Also, the clock signal is associated with at least a predetermined frequency. The predetermined frequency does not change if the input voltage changes from a first magnitude to a second magnitude. The first magnitude is different from the second magnitude. | 11-17-2011 |
| 20110316428 | SYSTEMS AND METHODS FOR CONTROLLING BRIGHTNESS OF COLD-CATHODE FLUORESCENT LAMPS WITH WIDE DIMMING RANGE AND ADJUSTABLE MINIMUM BRIGHTNESS - System and method for adjusting brightness of one or more cold-cathode fluorescent lamps. The system includes a voltage selector configured to receive a dimming voltage and a first threshold voltage and generate an output voltage. The output voltage is selected from a group consisting of the dimming voltage and the first threshold voltage. Additionally, the system includes an oscillator coupled to a first capacitor and configured to generate a ramp signal with the first capacitor, and a signal generator configured to receive the ramp signal and the output voltage and generate a first signal. The first signal corresponds to a lamp brightness level. Moreover, the system includes a brightness detector configured to receive the first signal and output a second signal. The second signal indicates whether the lamp brightness level is higher than a threshold brightness level. | 12-29-2011 |
| 20120268031 | SYSTEMS AND METHODS FOR DIMMING CONTROL WITH CAPACITIVE LOADS - System and method for dimming control. The system includes a system controller including a first controller terminal and a second controller terminal, a transistor including a first transistor terminal, a second transistor terminal and a third transistor terminal, and a resistor including a first resistor terminal and a second resistor terminal. The system controller is configured to generate a first signal at the first controller terminal based on an input signal and to generate a second signal at the second controller terminal based on the first signal. The first transistor terminal is coupled to the second controller terminal. The first resistor terminal is coupled to the second transistor terminal. The second resistor terminal is coupled to the third transistor terminal. The transistor is configured to receive the second signal at the first transistor terminal and to change between two conditions in response to the second signal. | 10-25-2012 |
| 20120326629 | SYSTEMS AND METHODS FOR INTELLIGENT CONTROL OF COLD-CATHODE FLUORESCENT LAMPS - System and method for driving one or more cold-cathode fluorescent lamps. For example, the method includes generating at least one drive signal associated with a signal frequency, the signal frequency being equal to a first predetermined frequency, receiving a current-sensing signal, the current-sensing signal being associated with a lamp current for the one or more cold-cathode fluorescent lamps in response to at least the first predetermined frequency, and determining whether the current-sensing signal is larger than a first threshold in magnitude, the current-sensing signal being related to the first predetermined frequency. Additionally, the method includes, if the current-sensing signal related to the first predetermined frequency is determined to be larger than the first threshold in magnitude at anytime during a first period of time, changing the signal frequency from the first predetermined frequency to a second predetermined frequency, the second predetermined frequency being different from the first predetermined frequency. | 12-27-2012 |
| Patent application number | Description | Published |
|---|
| 20120139044 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI wafer, which comprises a bottom semiconductor substrate, a first buried insulating layer on the bottom semiconductor substrate, and a first semiconductor layer on the first buried insulating layer; a source region and a drain region which are formed in a second semiconductor layer over the SOI wafer, wherein there is a second buried insulating layer between the second semiconductor layer and the SOI wafer; a channel region, which is formed in the second semiconductor layer and located between the source region and the drain regions; and a gate stack, which comprises a gate dielectric layer on the second semiconductor layer and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the first semiconductor substrate below the channel region, the backgate having a non-uniform doping profile, and the second buried insulating layer serving as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the polarity of dopants and/or the doping profile in the backgate. Leakage in the semiconductor device can be reduced. | 06-07-2012 |
| 20120139048 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI chip comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; source/drain regions formed in the semiconductor layer; a channel region formed in the semiconductor layer and located between the source/drain regions; and a gate stack comprising a gate dielectric layer on the semiconductor layer, and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the semiconductor substrate below the channel region, and the backgate has a non-uniform doping profile, and wherein the buried insulating layer serves as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the type of dopant and/or the doping profile in the backgate, and reduces a leakage current of the semiconductor device. | 06-07-2012 |
| 20120326231 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer, which comprises a semiconductor substrate, a buried insulator layer, and a semiconductor layer, the buried insulator layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulator layer; a gate stack, which is disposed on the semiconductor layer; a source region and a drain region, which are disposed in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which are disposed in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate disposed in the semiconductor substrate, and wherein the back gate comprises first, second and third compensation doping regions, the first compensation doping region is disposed under the source region and the drain region; the second compensation doping region extends in a direction away from the channel region and adjoining the first compensation doping region; and the third compensation doping region is disposed under the channel region and adjoining the first compensation doping region. By changing the doping type of the back gate, the MOSFET can have an adjustable threshold voltage, and can have a reduced parasitic capacitance and a reduced contact resistance in connection with the back gate. | 12-27-2012 |
| Patent application number | Description | Published |
|---|
| 20110092118 | Curable Aqueous Composition - A curable aqueous composition, a method for forming a treated substrate with the curable aqueous composition, and the substrate so treated are provided. The curable aqueous composition, the process for forming a treated substrate and the treated substrate may be free from formaldehyde. The curable aqueous composition includes: an emulsion polymer including, as copolymerized units, from 0.5 to 9% ethylenically-unsaturated dicarboxylic acid monomer by weight, based on the weight of the emulsion polymer; and a polyol in the amount of from 0.5 to 15%, by weight, based on the weight of the emulsion polymer, wherein the aqueous composition includes carboxylic acid-containing polymer including, as polymerized units, from 0.5 to 9% carboxylic acid monomer by weight, based on the total weight of the carboxylic acid-containing polymer. | 04-21-2011 |
| 20110152447 | Curable Aqueous composition - A curable aqueous composition, a method for forming a treated substrate with the curable aqueous composition, and the substrate so treated are provided. The composition, the method and the treated substrate may be free from formaldehyde. The composition comprises a (co)polymer and a crosslinker, said (co)polymer comprising, as (co)polymerized units, from 0.05 to 10 wt %, based on the dry weight of the composition, ethylenically unsaturated monomer having at least two carboxylic acid groups, wherein the crosslinker having at least two hydrazino groups having a molar ratio of at least 0.05 of the carboxylic acid group, and wherein the aqueous composition is curable at a temperature of from 100° C. to 250° C. | 06-23-2011 |
| 20120251822 | Clean Removable Adhesive Sheet - The invention provides an adhesive sheet comprising polyvinyl chloride (PVC) film and back coating of water based PSA, wherein said PSA comprises a copolymer by copolymerization of a monomer mixture comprising, a) from 30 wt % to less than 70 wt % acrylic acid C4-C8-alkylester, and b) from 2 wt % to 9 wt % (meth)acrylonitrile, wherein the polyvinyl chloride film is not corona treated. The adhesive sheet is suitable for applications of indoor and outdoor graphic poster, especially for clean removable usages. | 10-04-2012 |
| Patent application number | Description | Published |
|---|
| 20110310770 | COMMUNICATION METHOD FOR MESH AND STAR TOPOLOGY STRUCTURE WIRELESS SENSOR NETWORK - A method of achieving wireless sensor network (WSN) communication in a mesh and star topology network (MSTN), including: a) connecting a plurality of nodes in a WSN to form a mesh and star hybrid topology structure; b) based on the topology structure, defining a superframe structure based on IEEE 802.15.4-2006; c) based on the topology structure and superframe structure, defining methods for long period data processing, connectivity assessment, medium access control, channel measurement, frequency hopping, beacon frame formation, and two-stage resource allocation; d) based on the topology structure, superframe structure, and methods, defining a method for network establishment; and e) based on the network establishment method, defining a method for MSTN communications. The method features real-time communication, high reliability, and low energy consumption. | 12-22-2011 |
| 20120213062 | METHOD OF TWO-STAGE ADAPTIVE FREQUENCY HOPPING FOR CLUSTERED WIRELESS SENSOR NETWORK - A method of two-stage adaptive frequency hopping for a clustered wireless sensor network, including: a) building a clustered wireless sensor network; b) defining a superframe structure based on IEEE 802.15.4 according to a topology of the clustered wireless sensor network; c) extending a beacon frame payload based on a beacon frame format of an IEEE 802.15.4 Media Access Control (MAC) layer; and d) performing a two-stage adaptive frequency hopping mechanism on nodes based on the above superframe structure and the extended beacon frame of the IEEE 802.15.4 MAC layer. | 08-23-2012 |
| Patent application number | Description | Published |
|---|
| 20110248354 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects. | 10-13-2011 |
| 20110254013 | HYBRID ORIENTATION ACCUMULATION MODE GAA CMOSFET - A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased. | 10-20-2011 |
| 20110254099 | Hybrid material accumulation mode GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 10-20-2011 |
| 20110254100 | HYBRID MATERIAL ACCUMULATION MODE GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented. | 10-20-2011 |
| 20110254101 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 10-20-2011 |
| 20110254102 | HYBRID ORIENTATION INVERSION MODE GAA CMOSFET - A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects. | 10-20-2011 |
| 20120112283 | ESD PROTECTION DEVICES FOR SOI INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF - The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness. | 05-10-2012 |
| 20120129320 | METHOD OF NISIGE EPITAXIAL GROWTH BY INTRODUCING AL INTERLAYER - The present invention discloses a method of NiSiGe epitaxial growth by introducing Al interlayer, comprising the deposition of an Al thin film on the surface of SiGe layer, subsequent deposition of a Ni layer on Al thin film and then the annealing process for the reaction between Ni layer and SiGe material of SiGe layer to form NiSiGe material. Due to the barrier effect of Al interlayer, NiSiGe layer features a single crystal structure, a flat interface with SiGe substrate and a thickness of up to 0.3 nm, significantly enhancing interface performance. | 05-24-2012 |
