Patent application number | Description | Published |
20120150781 | INTEGRATE AND FIRE ELECTRONIC NEURONS - An integrate and fire electronic neuron is disclosed. Upon receiving an external spike signal, a digital membrane potential of the electronic neuron is updated based on the external spike signal. The electric potential of the membrane is decayed based on a leak rate. Upon the electric potential of the membrane exceeding a threshold, a spike signal is generated. | 06-14-2012 |
20130073497 | NEUROMORPHIC EVENT-DRIVEN NEURAL COMPUTING ARCHITECTURE IN A SCALABLE NEURAL NETWORK - An event-driven neural network includes a plurality of interconnected core circuits is provided. Each core circuit includes an electronic synapse array has multiple digital synapses interconnecting a plurality of digital electronic neurons. A synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. A neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. Each core circuit also has a scheduler that receives a spike event and delivers the spike event to a selected axon in the synapse array based on a schedule for deterministic event delivery. | 03-21-2013 |
20140092728 | FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON A PROCESSOR ARRAY - Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures. | 04-03-2014 |
20140095923 | FINAL FAULTY CORE RECOVERY MECHANISMS FOR A TWO-DIMENSIONAL NETWORK ON A PROCESSOR ARRAY - Embodiments of the invention relate to faulty recovery mechanisms for a two-dimensional (2-D) network on a processor array. One embodiment comprises a processor array including multiple processors core circuits, and a redundant routing system for routing packets between the core circuits. The redundant routing system comprises multiple switches, wherein each switch corresponds to one or more core circuits of the processor array. The redundant routing system further comprises multiple data paths interconnecting the switches, and a controller for selecting one or more data paths. Each selected data path is used to bypass at least one component failure of the processor array to facilitate full operation of the processor array. | 04-03-2014 |
20140114893 | LOW-POWER EVENT-DRIVEN NEURAL COMPUTING ARCHITECTURE IN NEURAL NETWORKS - A neural network includes an electronic synapse array of multiple digital synapses interconnecting a plurality of digital electronic neurons. Each synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. Each neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold. A decoder receives spike events sequentially and transmits the spike events to selected axons in the synapse array. An encoder transmits spike events corresponding to spiking neurons. A controller coordinates events from the synapse array to the neurons, and signals when neurons may compute their spike events within each time step, ensuring one-to-one correspondence with an equivalent software model. The synapse array includes an interconnecting crossbar that sequentially receives spike events from axons, wherein one axon at a time drives the crossbar, and the crossbar transmits synaptic events in parallel to multiple neurons. | 04-24-2014 |
20140180984 | TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A UNIVERSAL SUBSTRATE OF ADAPTATION - Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained. | 06-26-2014 |
20140180985 | MAPPING NEURAL DYNAMICS OF A NEURAL MODEL ON TO A COARSELY GRAINED LOOK-UP TABLE - Embodiments of the invention relate to mapping neural dynamics of a neural model on to a lookup table. One embodiment comprises defining a phase plane for a neural model. The phase plane represents neural dynamics of the neural model. The phase plane is coarsely sampled to obtain state transition information for multiple neuronal states. The state transition information is mapped on to a lookup table. | 06-26-2014 |
20140180987 | TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY ADDRESSING FOR IMPLEMENTING A NEURAL NETWORK - Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step. | 06-26-2014 |
20140180988 | HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS - Embodiments of the invention relate to a neural network system for simulating neurons of a neural model. One embodiment comprises a memory device that maintains neuronal states for multiple neurons, a lookup table that maintains state transition information for multiple neuronal states, and a controller unit that manages the memory device. The controller unit updates a neuronal state for each neuron based on incoming spike events targeting said neuron and state transition information corresponding to said neuronal state. | 06-26-2014 |
20140222740 | CONSOLIDATING MULTIPLE NEUROSYNAPTIC CORES INTO ONE MEMORY - Embodiments of the invention relate to a neural network system comprising a single memory block for multiple neurosynaptic core modules. One embodiment comprises a neural network system including a memory array that maintains information for multiple neurosynaptic core modules. Each neurosynaptic core module comprises multiple neurons. The neural network system further comprises at least one logic circuit. Each logic circuit receives neuronal firing events targeting a neurosynaptic core module of the neural network system, and said logic circuit integrates the firing events received based on information maintained in said memory for said neurosynaptic core module. | 08-07-2014 |
20140244971 | ARRAY OF PROCESSOR CORE CIRCUITS WITH REVERSIBLE TIERS - Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and multiple switches for routing packets between the core circuits. Each tier comprises at least one core circuit. Each switch comprises multiple router channels for routing packets in different directions relative to the switch, and at least one routing circuit configured for reversing a logical direction of at least one router channel. | 08-28-2014 |
20140344201 | PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING COLUMN AGGREGATION - Embodiments of the invention relate to providing transposable access to a synapse array using column aggregation. One embodiment comprises a neural network including a plurality of electronic axons, a plurality of electronic neurons, and a crossbar for interconnecting the axons with the neurons. The crossbar comprises a plurality of electronic synapses. Each synapse interconnects an axon with a neuron. The neural network further comprises a column aggregation module for transposable access to one or more synapses of the crossbar using column aggregation. | 11-20-2014 |
20150039546 | DUAL DETERMINISTIC AND STOCHASTIC NEUROSYNAPTIC CORE CIRCUIT - One embodiment provides a system comprising a memory device for maintaining deterministic neural data relating to a digital neuron and a logic circuit for deterministic neural computation and stochastic neural computation. Deterministic neural computation comprises processing a neuronal state of the neuron based on the deterministic neural data maintained. Stochastic neural computation comprises generating stochastic neural data relating to the neuron and processing the neuronal state of the neuron based on the stochastic neural data generated. | 02-05-2015 |