Patent application number | Description | Published |
20090161738 | Transceiver system with reduced latency uncertainty - A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner. | 06-25-2009 |
20090289660 | INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES - A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device. | 11-26-2009 |
20130007679 | RECONFIGURABLE LOGIC BLOCK - A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors. | 01-03-2013 |
20130007687 | METHOD AND SYSTEM FOR PARTIAL RECONFIGURATION SIMULATION - Disclosed is a method of simulating partial reconfiguration of a programmable logic device (PLD). A wrapper module is incorporated into a logic description that may be implemented in a PLD. The wrapper module represents a first logic design. In response to receiving a parameter, the wrapper module changes to represent a second logic design. According to various embodiments, the logic description is a simulatable source file. The simulatable source file is a source file that is used by a simulation program to simulate partial reconfiguration of the logic design. The wrapper module of the simulatable source file receives a run-time parameter. In various embodiments, the logic description is a synthesizable source file. The synthesizable source file is a source file that is used by a synthesis tool to compile the source file into hardware. The wrapper module of the synthesizable source receives a compile-time parameter. | 01-03-2013 |
20130207688 | Apparatus and Methods for Time-Multiplex Field-Programmable Gate Arrays - A time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry, programmable interconnect circuitry, and a plurality of context registers. A user's circuit can be mapped to the programmable logic circuitry, the programmable interconnect circuitry, and the plurality of context registers without the user's intervention in mapping the design. | 08-15-2013 |
20140047401 | RECONFIGURABLE LOGIC BLOCK - A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. An enable read flag is provided to indicate if values stored in the configuration logic are to be read out or a known state is to be read out during a data verification process. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state. Moreover, the region of configuration logic may be dynamically reconfigured from one state to another without causing verification errors. | 02-13-2014 |
20140097877 | SIGNAL FLOW CONTROL THROUGH CLOCK SIGNAL RATE ADJUSTMENTS - Control circuitry and adjustable clock signal generation circuitry is provided to control the signal transmission rate for electronic devices and systems of electronic devices. The control circuitry may receive status signals indicating current clock rates of a signal transmitting and receiving circuit as well as current processing capacity from the signal receiving circuit. The control circuitry may then generate control signals which control adjustable clock signal generation circuitry. The adjustable clock signal generation circuitry may be used to adjust the rate of generated clock signals for the signal transmitting and receiving circuits which can increase or decrease the signal transmission rate between those circuits. | 04-10-2014 |
20140119486 | APPARATUS FOR IMPROVED ENCODING AND ASSOCIATED METHODS - An apparatus includes an encoder adapted to encode data bits for transmission via a communication link using pulse amplitude modulation (PAM). The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length and/or improve the DC balance of the data bits. | 05-01-2014 |
20140198810 | METHODS AND APPARATUS FOR ALIGNING CLOCK SIGNALS ON AN INTEGRATED CIRCUIT - A method of aligning clock signals in multiple transceiver channels on an integrated circuit may include adjusting a slave clock signal at a slave transceiver channel based on a master clock signal received from a master transceiver channel. A clock generation circuit and/or a delay circuit in the slave transceiver channel may be used to adjust the slave clock signal to produce an intermediate slave clock signal. The master clock signal may be adjusted based on the intermediate slave clock signal received at the master transceiver channel to obtain a total adjustment value. The phase of the intermediate slave clock signal may further be adjusted at the slave transceiver channel based on the total adjustment made at the master transceiver channel. | 07-17-2014 |
20140269778 | METHODS TO ACHIEVE ACCURATE TIME STAMP IN IEEE 1588 FOR SYSTEM WITH FEC ENCODER - Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s) from forward error correction (FEC) sublayer changes in a data frame that is transmitted by the MAC layer. Feedback is provided to the MAC from the FEC to allow the MAC to accurately determine the timestamp point and timestamp value align preamble of the data frame to the beginning of the FEC bit block that is output by the FEC sublayer. | 09-18-2014 |
20140269983 | APPARATUS FOR IMPROVED COMMUNICATION AND ASSOCIATED METHODS - An apparatus includes a transmitter adapted to transmit encoded information to a communication link. The transmitter includes a DC balance skew generator. The DC balance skew generator is adapted to skew a DC balance of the information before information is provided to the communication link. | 09-18-2014 |
20150022236 | Apparatus and Methods for Time-Multiplex Field-Programmable Gate Arrays - A time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry, programmable interconnect circuitry, and a plurality of context registers. A user's circuit can be mapped to the programmable logic circuitry, the programmable interconnect circuitry, and the plurality of context registers without the user's intervention in mapping the design. | 01-22-2015 |
Patent application number | Description | Published |
20080270919 | Context Based Software Layer - A computer-implementable method, system and computer-readable medium for establishing and utilizing a widget-centric context-based layer are presented. In a preferred embodiment, the computer-implemented method includes a computer detecting a mouse hover over a visual control that is displayed on a visual layer canvas. In response to determining that the visual control is supported by a context layer, the computer displays the visual control and component icons on a context layer canvas, wherein the context layer includes elements from both an upper visual layer and a lower component layer, and wherein the component icons are associated with respective components from the lower component layer. The computer then receives a user input that selects one or more of the component icons, thus permitting associated components to be edited. | 10-30-2008 |
20120084752 | IMAGE ASSET LIFECYCLE MANAGEMENT IN A COMPUTING ENVIRONMENT - Lifecycles of virtual image assets are managed as follows. A set of assets including a set virtual image assets and a set of software bundle assets are analyzed. At least a portion of relationship data between one or more of the virtual image assets and one or more of the software bundle assets is determined. The at least a portion of relationship data is stored in a memory. At least one of one or more virtual image assets and one or more software bundle assets are determined to be associated with a set of changes. At least one virtual image asset that is related to the one or more virtual image assets and/or one or more software bundle assets associated with the set of changes is identified. The at least one virtual image asset that has been identified is updated based on the set of changes. | 04-05-2012 |
20120311468 | DYNAMIC INTERFACE COMPONENT CONTROL SUPPORT - A system, computer program and method for developing a graphical user interface (GUI) in a computer program. The invention allows developers to control the properties of interface components according to the state of a program during execution. According to the invention, a GUI development environment may be configured to provide a GUI builder for creating the GUI, display an interface component with at least one interface component property to be instantiated in the GUI, display a property interface to input at least one value for the interface component property in response to an event detectable by the computer program during GUI program execution, and automatically generate GUI program code effectuating the value for the interface component property in response to the event detectable by the computer program during GUI program execution. | 12-06-2012 |
20130007745 | IMAGE ASSET LIFECYCLE MANAGEMENT IN A COMPUTING ENVIRONMENT - Lifecycles of virtual image assets are managed as follows. A set of assets including a set virtual image assets and a set of software bundle assets are analyzed. At least a portion of relationship data between one or more of the virtual image assets and one or more of the software bundle assets is determined. The at least a portion of relationship data is stored in a memory. At least one of one or more virtual image assets and one or more software bundle assets are determined to be associated with a set of changes. At least one virtual image asset that is related to the one or more virtual image assets and/or one or more software bundle assets associated with the set of changes is identified. The at least one virtual image asset that has been identified is updated based on the set of changes. | 01-03-2013 |
20140007258 | SYSTEMS AND METHODS FOR GOVERNING THE DISCLOSURE OF RESTRICTED DATA | 01-02-2014 |
20140245067 | USING LINKED DATA TO DETERMINE PACKAGE QUALITY - Arrangements described herein relate to determining a quality of a software package. Via linked data, the software package can be linked to at least one test plan and a requirement collection. The software package can be executed in accordance with the test plan using at least one test case. At least one test result of the execution of the software package can be generated. A score can be assigned to the test result and a score can be assigned to the test based at least on the test result. Based at least the scores on assigned to the test result and the test case, a package quality score can be assigned to the software package. | 08-28-2014 |
20140245068 | USING LINKED DATA TO DETERMINE PACKAGE QUALITY - Arrangements described herein relate to determining a quality of a software package. Via linked data, the software package can be linked to at least one test plan and a requirement collection. The software package can be executed in accordance with the test plan using at least one test case. At least one test result of the execution of the software package can be generated. A score can be assigned to the test result and a score can be assigned to the test based at least on the test result. Based at least the scores on assigned to the test result and the test case, a package quality score can be assigned to the software package. | 08-28-2014 |
20140298413 | Mapping the Network File System (NFS) protocol to secure web-based applications - Users on a client system access files served by a web application through the Network File System (NFS) protocol using common web authentication mechanisms while still honoring constraints imposed by the application's authorization rules. To this end, the client system is modified to include an NFS server. Following authentication of the NFS server with the web application, NFS-based requests (from a local NFS client) directed to the application are received at the NFS server instead of being sent to the application directly. The NFS server, in turn, maps those requests to the web application preferably using standard HTTP. Because the web application's normal security model is enforced as intended at the web application, the approach enables individual users of the client system to operate under different visibility constraints dictated by the web application. Thus, fine-grained permissions may be enforced at the web application for different users. | 10-02-2014 |
20140324825 | GENERATION OF MULTI-FACETED SEARCH RESULTS IN RESPONSE TO QUERY - Aspects retrieve, organize and display different classifications of sets of search results in different, respective tabbed sheets that are nested on top of one another in a web-based interface dashboard. A text string search query is classified into constituent primary search terms that are likely to return satisfactory search results as indicated by retrieved search history data as a function of search resources and language classification rules associated with the user identity indicia. Secondary search terms related to the primary search terms and including synonyms and antonyms are determined as substitutes for the primary search terms in response to search history indicating follow-up searches immediately subsequent to searches of the primary search terms at less than a specified threshold of frequency. The set of peripheral knowledge article results is generated by searching knowledge article resources for background information on the primary search terms or the secondary search terms. | 10-30-2014 |