| Patent application number | Description | Published |
|---|
| 20090121028 | System and Method for Updating Read-Only Memory in Smart Card Memory Modules - A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions. One of these partitions may be a read-only partition that is normally accessible only for read accesses. However, it may sometimes be necessary to update or supplement the data stored in the read-only partition. This is accomplished by a host issuing an appropriate command to the storage device, which may be accompanied by an identifier for an appropriate level of authorization. The controller then changes the attribute of the read-only partition from “read-only” to “read/write” to allow data to be written to the partition. Upon completion, the controller changes the attribute of the partition back to read-only. | 05-14-2009 |
| 20090121029 | INTELLIGENT CONTROLLER SYSTEM AND METHOD FOR SMART CARD MEMORY MODULES - A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data in various partitions corresponding to the protection level of the data stored therein. The smart-card device stores critical security parameters that are provided to the controller to protect access to some or all of the partitions of the memory device. A host connected to the controller issues commands, and the controller analyzes the commands and responds to them in various ways depending upon the nature of the command. In particular, depending upon the nature of the command, the controller may either pass the command to the smart-card device, or ignore the command either indefinitely or until a predetermined event has occurred. | 05-14-2009 |
| 20090122989 | SMART STORAGE DEVICE - A smart storage device can have a smart-card portion with access control circuitry and integrated memory, a controller in selective communication with the smart-card portion, and a memory device in communication with the controller. The memory device can be separate from the smart-card portion and can store one or more smart-card applications. | 05-14-2009 |
| 20090125643 | SYSTEM AND METHOD FOR DRIVE RESIZING AND PARTITION SIZE EXCHANGE BETWEEN A FLASH MEMORY CONTROLLER AND A SMART CARD - A system and method to control a device having at least one configurable parameter. Enumerating the device as a first peripheral device and as a second peripheral device wherein the first peripheral device corresponds to a first microcontroller connected to a storage medium and the second peripheral device corresponds to a second microcontroller. Controlling the at least one configurable parameter of the first microcontroller with respect to the storage medium by the second microcontroller. On initialization of the device, transmitting the at least one configurable parameter from the second microcontroller to the first microcontroller. Other systems and methods are disclosed. | 05-14-2009 |
| 20090125645 | SYSTEM AND METHOD FOR SUPPORTING MULTIPLE TOKENS HAVING A SMART CARD TO CONTROL PARAMETERS OF A FLASH MEMORY DEVICE - A system and method to control a device having at least one configurable parameter. Enumerating the device as a first peripheral device and as a second peripheral device wherein the first peripheral device corresponds to a first microcontroller connected to a storage medium and the second peripheral device corresponds to a second microcontroller. Controlling the at least one configurable parameter of the first microcontroller with respect to the storage medium by the second microcontroller. On initialization of the device, transmitting the at least one configurable parameter from the second microcontroller to the first microcontroller. Other systems and methods are disclosed. | 05-14-2009 |
| 20090271533 | METHOD AND APPARATUS FOR FIELD FIRMWARE UPDATES IN DATA STORAGE SYSTEMS - Data storage devices and methods for updating firmware are disclosed. For example, one such data storage device includes a device firmware and a controller, where the controller operates in accordance with the device firmware. The controller determines whether or not the device firmware can be updated with new firmware at least partially based on whether or not the new firmware meets a criterion related to a configuration profile of the device firmware. | 10-29-2009 |
| 20100023650 | SYSTEM AND METHOD FOR USING A SMART CARD IN CONJUNCTION WITH A FLASH MEMORY CONTROLLER TO DETECT LOGON AUTHENTICATION - A system and method of operating a device connected to a host computer in a manner to preserve knowledge of logon authentication status to the host computer. Upon initialization of the device perform a pattern matching operation of an instruction sequence received by the second microcontroller. When the instruction sequence matches a prestored sequence indicative of performance of a logon process on the host computer tracking a logon state by the second microcontroller. Exchanging the logon state between the second and first microcontrollers such that when the second microcontroller resets, the second microcontroller may recover the logon state from the first microcontroller. Other systems and methods are disclosed. | 01-28-2010 |
| 20100023747 | Critical Security Parameter Generation and Exchange System and Method for Smart-Card Memory Modules - A storage device contains a smart-card device and a memory device, which is connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may be used to store a relatively large amount of data. The memory device may also be used to store data or instructions for use by the smart-card device. The controller includes a security engine that uses critical security parameters stored in, and received from, the smart-card device. The critical security parameters may be sent to the controller in a manner that protects them from being discovered. The critical security parameters may be encryption and/or decryption keys that may encrypt data written to the memory device and/or decrypt data read from the memory device, respectively. Data and instructions used by the smart-card device may therefore stored in the memory device in encrypted form. | 01-28-2010 |
| 20100023777 | SYSTEM AND METHOD FOR SECURE FIRMWARE UPDATE OF A SECURE TOKEN HAVING A FLASH MEMORY CONTROLLER AND A SMART CARD - A system and method of operating a device to securely update the control firmware controlling the device. Downloading a firmware update package to a first microcontroller of the device. Determining a firmware update portion and an encrypted hash portion of the firmware update package wherein the encrypted hash portion is cryptographically signed by a signatory. Confirm that the encrypted hash portion conforms to the firmware update by independently computing the hash of the encrypted firmware update portion on the first microcontroller and comparing that value to the signed hash. Other systems and methods are disclosed. | 01-28-2010 |
| 20100077117 | SATA MASS STORAGE DEVICE EMULATION ON A PCIe INTERFACE - A mass storage device, system, and method for operating a mass storage device are disclosed. In one such mass storage device, a host bus adaptor emulates a SATA mass storage device over a PCIe interface with a host system. The host system generates commands with the PCIe mass storage device in the same format as if communicating with a SATA mass storage device. The PCIe mass storage device responds in the same SATA format. | 03-25-2010 |
| 20100115116 | SYSTEM AND METHOD FOR SWITCHING COMMUNICATION PROTOCOLS IN ELECTRONIC INTERFACE DEVICES - Methods and systems are disclosed including those that cause an electronic interface device to dynamically switch protocols that it uses to communicate with a host to which the electronic interface device is connected. In one such embodiment, the electronic interface device first attempts using a first communications protocol, such as a CCID protocol. If the host contains a driver for the first communications protocol, the host communicates with the electronic interface device using the first communications protocol. If the host does not contain a driver for the first communications protocol, the electronic interface device attempts using a second communications protocol that is different from the first communications protocol, such as a HID protocol. The host then communicates with the electronic interface device using the second communications protocol. If the electronic interface device communicates with the host using the first communications protocol, it may transmit user authentication data, such as a password, to the host. | 05-06-2010 |
| 20100153747 | PARALLEL ENCRYPTION/DECRYPTION - The present disclosure includes methods and devices for parallel encryption/decryption. In one or more embodiments, an encryption/decryption device includes an input logic circuit, an output logic circuit, and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit. For example, each encryption/decryption circuit can be capable of processing data at an encryption/decryption rate, and the number of encryption/decryption circuits can be equal to or greater than an interface throughput rate divided by the encryption/decryption rate. | 06-17-2010 |
| 20100180105 | MODIFYING COMMANDS - The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured to modify at least a number of commands in the queue and execute the modified commands. | 07-15-2010 |
| 20100185802 | SOLID STATE MEMORY FORMATTING - The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary. | 07-22-2010 |
| 20100185830 | LOGICAL ADDRESS OFFSET - The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address. | 07-22-2010 |
| 20100199134 | DETERMINING SECTOR STATUS IN A MEMORY DEVICE - The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. A number of method embodiments include reading data from memory cells corresponding to a sector of data, determining a number of the memory cells in a non-erased state, and, if the number of the memory cells in a non-erased state is less than or equal to a number of errors correctable by an ECC engine, determining the sector is erased. | 08-05-2010 |
| 20100211834 | DATA INTEGRITY IN MEMORY CONTROLLERS AND METHODS - The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface. | 08-19-2010 |
| 20100228928 | MEMORY BLOCK SELECTION - The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation. | 09-09-2010 |
| 20100228940 | MEMORY BLOCK MANAGEMENT - Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective. | 09-09-2010 |
| 20100229004 | PROTECTION OF SECURITY PARAMETERS IN STORAGE DEVICES - Security parameters used to encrypt data stored on a storage device may be protected using embodiments of systems and methods described herein. During a resize operation, data stored on a memory unit in the storage device may be altered prior to communicating an updated partition size to a host computer. In some examples, data is altered prior to storing the updated partition sizes in the storage device. In this manner, a host system may not receive the updated partition sizes until after the data is altered. Altering data may avoid exposure encrypted data, information about one or more security parameters used to encrypt data on the memory unit or decrypt data retrieved from the memory unit, or combinations thereof. | 09-09-2010 |
| 20100262721 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 10-14-2010 |
