| Patent application number | Description | Published |
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| 20080201604 | Kernel Error Recovery Disablement and Shared Recovery Routine Footprint Areas - A method, computer program product, and data processing system for providing optional failure recovery features in operating system kernel code are disclosed. In accordance with a preferred embodiment, a segment of mainline code may designate a recovery routine for that segment by calling a kernel service provided for that purpose. The kernel service allocates a “footprint” region on the recovery stack for storing state information arising from the execution of the recovery-enabled code. In the event of an exception, a recovery manager routine uses information from the recovery stack to recover from the exception. Recovery may be disabled altogether for performance purposes by way of boot-time patching to disable the use of the recovery stack and to allow state information to be written to a static “scratchpad” area, which unlike the recovery stack, is allowed to be overwritten, its contents being ignored. | 08-21-2008 |
| 20080201606 | Recovery Routine Masking and Barriers to Support Phased Recovery Development - A method, computer program product, and data processing system for providing optional exception recovery features in operating system kernel code are disclosed. In a preferred embodiment, a segment of mainline code may designate a recovery routine for that segment by calling a kernel service provided for that purpose. The kernel service pushes the address of the designated recovery routine, context, and re-entry point information corresponding to the segment to a recovery stack. An additional “footprint” region is also allocated on the recovery stack and used to store other state information needed for recovery. A mask value or barrier count value is also stored on the recovery stack to allow recovery to be disabled for non-recoverable routines. | 08-21-2008 |
| 20080263301 | KEY-CONTROLLED OBJECT-BASED MEMORY PROTECTION - A method, system, and program key-controlled object-based memory protection are provided. A processing unit includes an authority check for controlling access by the processing unit to pages of memory according to whether a hardware protection key set currently loaded in an authority mask register allows access to the pages. In particular, each page of memory is assigned a page key number that indexes into the hardware protection key set. The currently loaded hardware protection key set specifies those page key numbers that are currently accessible to the processing unit for the execution context. Each hardware key within the hardware protection key set may be associated with a particular data object or group of data objects. Thus, effectively, the currently loaded hardware protection key set identifies which data objects or groups of data objects are currently accessible. Software keys are assigned to data objects and dynamically mapped to hardware protection key sets, such that when a module is called, the software keys assigned to that module are mapped to the hardware protection key set to be loaded for controlling current access to memory. | 10-23-2008 |
| 20100115522 | MECHANISM TO CONTROL HARDWARE MULTI-THREADED PRIORITY BY SYSTEM CALL - A method, a system and a computer program product for controlling the hardware priority of hardware threads in a data processing system. A Thread Priority Control (TPC) utility assigns a primary level and one or more secondary levels of hardware priority to a hardware thread. When a hardware thread initiates execution in the absence of a system call, the TPC utility enables execution based on the primary level. When the hardware thread initiates execution within a system call, the TPC utility dynamically adjusts execution from the primary level to the secondary level associated with the system call. The TPC utility adjusts hardware priority levels in order to: (a) raise the hardware priority of one hardware thread relative to another; (b) reduce energy consumed by the hardware thread; and (c) fulfill requirements of time critical hardware sections. | 05-06-2010 |
| 20110022895 | Software Component Self-Scrubbing - Software components “self-scrub” to improve software reliability, serviceability and availability (RAS). Each component designates a routine to perform a component level consistency check on major data structures and to verify the state of component. This is performed as an on-going task during the life of the component. The component registers an entry point with the system to receive notification of scrubbing parameter changes. The entry point is also called with the request to perform component-scrubbing operations. The entry point functions are responsible for executing within limitations on central processing unit (CPU) usage and memory footprint when performing scrubbing operations. | 01-27-2011 |
| Patent application number | Description | Published |
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| 20080288807 | SYSTEM, METHOD, AND COMPUTER PROGRAM FOR PRESENTING AND UTILIZING FOOTPRINT DATA AS A DIAGNOSTIC TOOL - A data processing system for storing and identifying footprint data in a data processing system enabling automated collection, identification and formatting recovery of footprint data executing on a mainline routine. A footprint area is allocated onto a failure recovery routine stack for use by the mainline routine for storing footprint data. The mainline routine stores footprint data within the first footprint area. The data processing system can then receive a request from a diagnostic tool, where the request includes at least one search parameter. The data processing system can output any footprint data to a diagnostic tool corresponding to the search parameters in the request. | 11-20-2008 |
| 20080294864 | MEMORY CLASS BASED HEAP PARTITIONING - The illustrative embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a heap. The heap is partitioned into at least one sub heap based on a relationship to at least one memory class of a plurality of memory classes. A memory allocation request comprising a memory class is received from a requester. A unique heap handle based on the memory class and associated with a specific sub heap is generated. The unique heap handle is then returned to the requester. | 11-27-2008 |
| 20080295081 | FRAMEWORK FOR CONDITIONALLY EXECUTING CODE IN AN APPLICATION USING CONDITIONS IN THE FRAMEWORK AND IN THE APPLICATION - A computer implemented method, apparatus, and computer usable program code for returning a return code to an error hook in an application using a framework. An identifier and a pass-through are received from the error hook. The error hook is software code in the application. The pass-through is a set of parameters. If the identifier has an active status, a set of framework conditions is retrieved using the identifier. If the set of framework conditions is met, an inject callback is retrieved using the error identifier. The inject callback is called with the error identifier and the pass-through. An inject callback return code is received. If the inject callback return code is an execute return code, the execute return code is returned to the error hook. | 11-27-2008 |
| 20080307182 | EFFICIENT AND FLEXIBLE MEMORY COPY OPERATION - A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline. | 12-11-2008 |
| 20090138664 | CACHE INJECTION USING SEMI-SYNCHRONOUS MEMORY COPY OPERATION - A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory. | 05-28-2009 |
| 20090144737 | DYNAMIC SWITCHING OF MULTITHREADED PROCESSOR BETWEEN SINGLE THREADED AND SIMULTANEOUS MULTITHREADED MODES - An apparatus and program product utilize a multithreaded processor having at least one hardware thread among a plurality of hardware threads that is capable of being selectively activated and deactivated responsive to a control circuit. The control circuit additionally provides the capability of controlling how an inactive thread can be activated after the thread has been deactivated, e.g., by enabling or disabling reactivation in response to an interrupt. | 06-04-2009 |
| 20090182968 | VALIDITY OF ADDRESS RANGES USED IN SEMI-SYNCHRONOUS MEMORY COPY OPERATIONS - A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed. | 07-16-2009 |
