Mcteer
Allen Mcteer, Boise, ID US
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20120108042 | Methods Of Forming Doped Regions In Semiconductor Substrates - Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant. | 05-03-2012 |
20140054677 | Arrays Comprising Vertically-Oriented Transistors, Integrated Circuitry Comprising A Conductive Line Buried In Silicon-Comprising Semiconductor Material, Methods Of Forming A Plurality Of Conductive Lines Buried In Silicon-Comprising Semiconductor Material, And Methods Of Forming An Array Comprising Vertically-Oriented Transistors - An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The data/sense line has silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb. The conductively-doped semiconductor material of the data/sense line includes a conductivity-neutral dopant between the transistors in that column. Methods are disclosed. | 02-27-2014 |
20140054678 | N-type Field Effect Transistors, Arrays Comprising N-type Vertically-Oriented Transistors, Methods Of Forming An N-type Field Effect Transistor, And Methods Of Forming An Array Comprising Vertically-Oriented N-type Transistors - An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region there-between. At least one of the source/drain regions is conductively doped n-type with at least one of As and P. A conductivity-neutral dopant is in the silicon-comprising semiconductor material in at least one of the channel region and the at least one source/drain region. A gate construction is operatively proximate the channel region. Methods are disclosed. | 02-27-2014 |
Allen Mcteer, Meridian, ID US
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20080210921 | Silver selenide film stoichiometry and morphology control in sputter deposition - A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The method includes depositing silver-selenide using a sputter deposition process at a pressure of about 0.3 mTorr to about 10 mTorr. In accordance with one aspect of the invention, an RF sputter deposition process may be used preferably at pressures of about 2 mTorr to about 3 mTorr. In accordance with another aspect of the invention, a pulse DC sputter deposition process may be used preferably at pressures of about 4 mTorr to about 5 mTorr. | 09-04-2008 |
20090098717 | CO-SPUTTER DEPOSITION OF METAL-DOPED CHALCOGENIDES - The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge | 04-16-2009 |
Allen Mcteer US
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20090321943 | SEED LAYER FOR REDUCED RESISTANCE TUNGSTEN FILM - Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed. | 12-31-2009 |
Elizabeth A. Mcteer, Austin, TX US
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20090323963 | Methods and Media for Recovering Lost Encryption Keys - An information handing system provides a method for recovering encryption keys. The method includes providing a first recording medium of a plurality of recording media in a first drive of a plurality of drives. A first key is requested from a primary key manager (PKM) associated with the first drive, wherein the first drive provides a first key identifier (ID) to the PKM. If it is determined that the PKM provides the first key corresponding to the first key ID, a first identifying information for the PKM is stored in a memory for the first recording medium. | 12-31-2009 |
20150036236 | System and Method for Calculating Data Compression Ratio without Writing Data to Media - An information handling system includes a host processor and a tape drive, which in turn includes a controller and a compression buffer. The controller is in communication with the host processor, and is configured to receive a diagnostic command from the host processor, to switch the tape drive from a normal mode to a diagnostic mode in response to the diagnostic command, and to send a compression ratio for data associated with a write command to the host processor. The compression buffer is in communication with the controller, the compression buffer configured to receive the write command, to compress data associated with the write command while in the diagnostic mode, to calculate the compression ratio for the data associated with the write command, and to delete the compressed data while the tape drive is in the diagnostic mode. | 02-05-2015 |
20150331631 | System and Method for Calculating Data Compression Ratio without Writing Data to Media - An information handling system includes a host processor and a tape drive, which in turn includes a controller and a compression buffer. The controller is in communication with the host processor, and is configured to receive a diagnostic command from the host processor, to switch the tape drive from a normal mode to a diagnostic mode in response to the diagnostic command, and to send a compression ratio for data associated with a write command to the host processor. The compression buffer is in communication with the controller, the compression buffer configured to receive the write command, to compress data associated with the write command while in the diagnostic mode, to calculate the compression ratio for the data associated with the write command, and to delete the compressed data while the tape drive is in the diagnostic mode. | 11-19-2015 |
20150380032 | SYSTEMS AND METHODS FOR WRITING DATA TO BOTH SIDES OF SEQUENTIAL STORAGE MEDIA - In accordance with embodiments of the present disclosure, a sequential storage media system for writing to both sides of a sequential storage medium, may include a first head and a second head. The first head may be configured to maintain contact with a first side of the sequential storage medium and read data from and/or write data to the first side as the sequential storage medium is wound between reels for winding the sequential storage medium. The second head may be configured to maintain contact with a second side of the sequential storage medium and read data from and/or write data to the second side as the sequential storage medium is wound between reels for winding the sequential storage medium. | 12-31-2015 |
Everett A. Mcteer, Eagle, ID US
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20110315543 | FORMING MEMORY USING HIGH POWER IMPULSE MAGNETRON SPUTTERING - Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron sputtering (HIPIMS), wherein the resistive memory material is formed on the structure in an environment having a temperature of approximately 400 degrees Celsius or less. | 12-29-2011 |
20140268991 | CHALCOGENIDE MATERIAL AND METHODS FOR FORMING AND OPERATING DEVICES INCORPORATING THE SAME - Embodiments disclosed herein may relate to a memory cell comprising a chalcogenide material mixture having a chalcogenide composition and a metallic glass-forming composition. | 09-18-2014 |
20160064666 | MEMORY CELLS INCLUDING DIELECTRIC MATERIALS, MEMORY DEVICES INCLUDING THE MEMORY CELLS, AND METHODS OF FORMING SAME - A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described. | 03-03-2016 |
Everett Allen Mcteer, Eagle, ID US
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20110291147 | OHMIC CONTACTS FOR SEMICONDUCTOR STRUCTURES - A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAl | 12-01-2011 |
20140234996 | OHMIC CONTACTS FOR SEMICONDUCTOR STRUCTURES - A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAl | 08-21-2014 |
20150318038 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall. | 11-05-2015 |
20150318467 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner. | 11-05-2015 |
20150318468 | PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS - Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner. | 11-05-2015 |
Everett Allen Mcteer, Boise, ID US
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20160093688 | SOURCE-CHANNEL INTERACTION IN 3D CIRCUIT - A multilayer source provides charge carriers to a multitier channel connector. The source includes a metal silicide layer on a substrate and a metal nitride layer between the metal silicide layer and the channel. The metal silicide and the metal nitride are processed without an intervening oxide layer between them. In one embodiment, the source further includes a silicon layer between the metal nitride layer and the channel. The silicon layer can also be processed without an intervening oxide layer. Thus, the source does not have an intervening oxide layer from the substrate to the channel. | 03-31-2016 |