Patent application number | Description | Published |
20100318509 | METHODS AND SOFTWARE FOR ANALYSIS OF RESEARCH PUBLICATIONS - In one aspect, the invention comprises a computer system for searching databases and displaying search results, comprising databases storing information regarding publications and authors comprising author, title, date of publication, cited references, and citing references data; and Internet servers in communication with those databases; wherein at least one of those Internet servers is in communication with and operable to transmit data to a Web browser resident on a user's computer, and wherein the data is sufficient to enable the browser to display a citation overview page comprising: (a) a list of one or more titles of publications or names of authors, and (b) one or more displayed numerals representing how many publications in one or more specified categories cite to each of the publications, or, for author names, how many publications in one or more specified categories cite to publications on which those names are listed as authors. | 12-16-2010 |
20120047127 | METHODS AND SOFTWARE FOR ANALYSIS OF RESEARCH PUBLICATIONS - In one aspect, the invention comprises a computer system for searching databases and displaying search results, comprising databases storing information regarding publications and authors comprising author, title, date of publication, cited references, and citing references data; and Internet servers in communication with those databases; wherein at least one of those Internet servers is in communication with and operable to transmit data to a Web browser resident on a user's computer, and wherein the data is sufficient to enable the browser to display a citation overview page comprising: (a) a list of one or more titles of publications or names of authors, and (b) one or more displayed numerals representing how many publications in one or more specified categories cite to each of the publications, or, for author names, how many publications in one or more specified categories cite to publications on which those names are listed as authors. | 02-23-2012 |
Patent application number | Description | Published |
20110072307 | METHODS AND APPARATUSES FOR GENERATING NETWORK TEST PACKETS AND PARTS OF NETWORK TEST PACKETS - Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure. | 03-24-2011 |
20110173498 | Methods and Apparatuses for Generating Network Test Packets and Parts of Network Test Packets - Some aspects of the technology relate to the generation for test purposes of test packet ingredients by a microprocessor, ongoing with the generation for test purposes of test packets incorporating the test packet ingredients by a high-speed FPGA. Some aspects of the technology relate to the generation of outgoing test packets incorporating the test packet ingredients, at a programmable logic device such as an FPGA. These aspects are implemented as an apparatus, a method, computer readable medium, and a data structure. | 07-14-2011 |
20140331075 | TIME REFERENCE SYSTEMS FOR CPU-BASED AND OPTIONALLY FPGA-BASED SUBSYSTEMS - A time reference system includes a master clock, generating a clock reference, interface logic and a CPU-based subsystem. The interface logic receives the clock reference and generates the clock, pulses, and timestamp signals. The CPU-based subsystem includes an internal counter, a CPU and a clock synthesizer, the CPU and receiving the pulses and timestamp signals. The clock synthesizer receives the clock signal and generates a CPU clock signal. Some examples include an FPGA-based subsystem having an FPGA-based card coupled to the interface logic for receipt of the clock, pulses and timestamp signals. In a method the timestamp value TO is generated by the CPU upon receipt of the timestamp signal. Upon receipt by the CPU of the next pulse signal, a timestamp counter baseline value TSCO is generated so the CPU internal counter is calibrated to the clock signal. | 11-06-2014 |
20150074770 | SECURE AUTHORIZATION OF MODULES RUNNING ON VIRTUALIZED HARDWARE - A method is described that includes securing authorization for a control module to conduct a test using a plurality of test modules running on a plurality of virtual machines. The method further includes registering the plurality of test modules with the control module to conduct the test. Authorization of the control module is extended to the test modules by securely communicating authorization and instructions to a first set of the registered test modules to send test stimulus to a device under test. Similarly, the authorization is extended to the test modules by securely communicating authorization to and receiving test result data from a second set of the registered test modules, wherein the test result data is responsive to the test stimulus sent to the device under test. The first and second sets of registered test modules can overlap or be the same test modules. | 03-12-2015 |