Patent application number | Description | Published |
20080299340 | OVER-MOLDED THICK WALL PARTS - An over-molded thick wall part, an insert used in forming the over-molded thick wall part, and a method of forming over-molded thick wall parts. The insert includes at least two sides, wherein one of the sides includes a flat surface. With a flat surface, there is a tendency to form sink marks rather than internal shrinkage voids to compensate for the volumetric shrinkage of the resin. Therefore, the flat surface enables the insert to cool without forming voids within the interior of the insert that may adversely affect the aesthetics and/or usefulness of the of the over-molded thick wall part. The cooled insert is then encompassed within an over-molded outer component to form the thick wall part. By using a two step molding process to form the thick wall part, substantial time and/or energy savings may be achieved as compared to prior art methods of forming thick wall parts. Depending on the types of materials used to form the insert and the outer component of the thick wall part, various parts may be formed including lenses, handles, housings and the like. | 12-04-2008 |
20100174031 | SYNTHETIC RESIN PROCESS AND ARTICLE USEFUL FOR PLATING APPLICATIONS - A method for processing reinforcing filler-filled synthetic resins and applications made therefrom wherein the resulting articles have the ability to be plated to form a structurally aesthetic product substantially free of visual defects. The process utilizes an accelerated heat and cool process to form a resin-rich surface that is substantially free of any reinforcing fillers, such as fiber strands and/or bundles, on the external surface of the article. As such, the resulting article is capable of being plated to form an article that is substantially free of visual defects caused by these fillers on the surface of the article. | 07-08-2010 |
20140024772 | SYNTHETIC RESIN PROCESS AND ARTICLE USEFUL FOR PLATING APPLICATIONS - A method for processing reinforcing filler-filled synthetic resins and applications made therefrom wherein the resulting articles have the ability to be plated to form a structurally aesthetic product substantially free of visual defects. The process utilizes an accelerated heat and cool process to form a resin-rich surface that is substantially free of any reinforcing fillers, such as fiber strands and/or bundles, on the external surface of the article. As such, the resulting article is capable of being plated to form an article that is substantially free of visual defects caused by these fillers on the surface of the article. | 01-23-2014 |
Patent application number | Description | Published |
20100321012 | DRIVE COIL, MEASUREMENT PROBE COMPRISING THE DRIVE COIL AND METHODS UTILIZING THE MEASUREMENT PROBE - The invention provides a drive coil and measurement probe comprising the drive coil. The measurement probes can be used, for example, in in-situ, non-destructive testing methods, also provided herein. | 12-23-2010 |
20110135872 | IN-LINE INSPECTION METHODS AND CLOSED LOOP PROCESSES FOR THE MANUFACTURE OF PREPREGS AND/OR LAMINATES COMPRISING THE SAME - In-line inspection methods are provided. The methods comprise measuring at least two parameters/properties of a prepreg and/or laminate during the manufacture thereof. In some embodiments, the data collected using the inline inspection methods may be processed and/or provided to a manual or automated controller, in order to provide a closed loop method for the manufacture of the prepregs and/or laminates. Apparatus for carrying out the methods are also provided, as are articles comprising a prepreg and/or laminate made using the apparatus. | 06-09-2011 |
20110215799 | MAGNETIC INSPECTION SYSTEMS FOR INSPECTION OF TARGET OBJECTS - Inspection systems provided herein may include a drive coil capable of being excited to generate a substantially uniform magnetic field about an object. The object includes a ferromagnetic adhesive adhered thereto. The inspection systems may also include an array of sensor coils adapted to detect the magnetic field from the drive coil after the magnetic field interacts with the ferromagnetic adhesive and to produce a voltage output corresponding to the detected magnetic field. | 09-08-2011 |
20130096853 | SYSTEMS AND METHODS FOR MONITORING ELECTRICAL CONTACTS - Systems and methods for monitoring electrical contacts are provided. One method includes calculating an impedance of an electrical contact based on an electrical signal applied to the electrical contact and a measured electrical signal after passing through the electrical contact. The method also includes determining a condition of the electrical contact using the calculated impedance. | 04-18-2013 |
20130104648 | TORSIONAL SENSOR INCLUDING A HIGH-PRESSURE SEALING MECHANISM AND SYSTEM FOR MEASUREMENT OF FLUID PARAMETERS | 05-02-2013 |
20140139211 | MAGNETIC INSPECTION SYSTEMS FOR INSPECTION OF TARGET OBJECTS - Inspection systems provided herein include drive coils capable of being excited to generate a substantially uniform magnetic field about an object. The object includes a ferromagnetic adhesive adhered thereto. The inspection systems may also include an array of sensor coils adapted to detect the magnetic field from the drive coils after the magnetic field interacts with the ferromagnetic adhesive and to produce a voltage output corresponding to the detected magnetic field. | 05-22-2014 |
Patent application number | Description | Published |
20100268885 | SPECIFYING AN ACCESS HINT FOR PREFETCHING LIMITED USE DATA IN A CACHE HIERARCHY - A system and method for specifying an access hint for prefetching limited use data. A processing unit receives a data cache block touch (DCBT) instruction having an access hint indicating to the processing unit that a program executing on the data processing system may soon access a cache block addressed within the DCBT instruction. The access hint is contained in a code point stored in a subfield of the DCBT instruction. In response to detecting that the code point is set to a specific value, the data addressed in the DCBT instruction is prefetched into an entry in the lower level cache. The entry may then be updated as a least recently used entry of a plurality of entries in the lower level cache. In response to a new cache block being fetched to the cache, the prefetched cache block is cast out of the cache. | 10-21-2010 |
20100268886 | SPECIFYING AN ACCESS HINT FOR PREFETCHING PARTIAL CACHE BLOCK DATA IN A CACHE HIERARCHY - A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache. | 10-21-2010 |
20110208949 | HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION - A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled. | 08-25-2011 |
20110296148 | Transactional Memory System Supporting Unbroken Suspended Execution - Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued. | 12-01-2011 |
20120084477 | Transactional Memory Preemption Mechanism - Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction. | 04-05-2012 |
20120185678 | HARDWARE THREAD DISABLE WITH STATUS INDICATING SAFE SHARED RESOURCE CONDITION - A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled. | 07-19-2012 |
20120246658 | Transactional Memory Preemption Mechanism - Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction. | 09-27-2012 |
20140013055 | ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES - A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction. | 01-09-2014 |
20140013060 | ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES - A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction. | 01-09-2014 |
20140040551 | REWIND ONLY TRANSACTIONS IN A DATA PROCESSING SYSTEM SUPPORTING TRANSACTIONAL STORAGE ACCESSES - In a multiprocessor data processing system having a distributed shared memory system, a memory transaction that is a rewind-only transaction (ROT) and that includes one or more transactional memory access instructions and a transactional abort instruction is executed. In response to execution of the one or more transactional memory access instructions, one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions are performed. In response to execution of the transactional abort instruction, execution results of the one or more transaction memory access instructions are discarded and control is passed to a fail handler. | 02-06-2014 |
20140040557 | NESTED REWIND ONLY AND NON REWIND ONLY TRANSACTIONS IN A DATA PROCESSING SYSTEM SUPPORTING TRANSACTIONAL STORAGE ACCESSES - In a multiprocessor data processing system having a distributed shared memory system, first and second nested memory transactions are executed, where the first memory transaction is a rewind-only transaction (ROT) and the second memory transaction is a non-ROT memory transaction. The first memory transaction has a transaction body including the second memory transaction and an additional plurality of transactional memory access instructions. In response to execution of the transactional memory access instructions, memory accesses are performed to the distributed shared memory system. Conflicts between memory accesses not within the first memory transaction and at least a load footprint of any of the transactional memory access instructions preceding the second memory transaction are not tracked. However, conflicts between memory accesses not within the first memory transaction and store and load footprints of any of the transactional memory access instructions that follow initiation the second memory transaction are tracked. | 02-06-2014 |
20140047195 | TRANSACTION CHECK INSTRUCTION FOR MEMORY TRANSACTIONS - A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction. | 02-13-2014 |
20140047196 | TRANSACTION CHECK INSTRUCTION FOR MEMORY TRANSACTIONS - A processing unit of a data processing system having a shared memory system executes a memory transaction including a transactional store instruction that causes a processing unit of the data processing system to make a conditional update to a target memory block of the shared memory system conditioned on successful commitment of the memory transaction. The memory transaction further includes a transaction check instruction. In response to executing the transaction check instruction, the processing unit determines, prior to conclusion of the memory transaction, whether the target memory block of the shared memory system was modified after the conditional update caused by execution of the transactional store instruction. In response to determining that the target memory block has been modified, a condition register within the processing unit is set to indicate a conflict for the memory transaction. | 02-13-2014 |
20140047205 | INTERACTION OF TRANSACTIONAL STORAGE ACCESSES WITH OTHER ATOMIC SEMANTICS - In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail. | 02-13-2014 |
20140075131 | METHOD AND APPARATUS FOR DETERMINING FAILURE CONTEXT IN HARDWARE TRANSACTIONAL MEMORIES - A processor core includes a transactional memory that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions in to the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions. | 03-13-2014 |
20140075132 | METHOD AND APPARATUS FOR DETERMINING FAILURE CONTEXT IN HARDWARE TRANSACTIONAL MEMORIES - A method for diagnosing an aborted transaction from a plurality of transactions is executed by a processor core with a transactional memory, that stores information corresponding to a plurality of transactions executed by the processor core, and a transaction diagnostic register. The processor core retrieves context summary information from at least one register of the processor core. The processor core stores the context summary information of aborted transactions in to the transactional memory or the transaction diagnostic register. The context summary information can be used for diagnosing the aborted transactions. | 03-13-2014 |
20140075441 | METHOD AND APPARATUS FOR RECORDING AND PROFILING TRANSACTION FAILURE SOURCE ADDRESSES IN HARDWARE TRANSACTIONAL MEMORIES - A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction. | 03-13-2014 |
20140081936 | METHOD AND APPARATUS FOR RECORDING AND PROFILING TRANSACTION FAILURE SOURCE ADDRESSES IN HARDWARE TRANSACTIONAL MEMORIES - A method for recording and profiling information of a plurality of aborted transactions from a plurality of transactions is executed by processor core with a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction. | 03-20-2014 |
20140115590 | METHOD AND APPARATUS FOR CONDITIONAL TRANSACTION ABORT AND PRECISE ABORT HANDLING - A method for executing a transaction in a data processing system initiates the transaction by a transactional-memory system coupled to that memory component. The method includes initiating the transaction by a transactional-memory system that is part of a memory component of the data processing system. The transaction includes instructions for comparing multiple parameters, and aborting the transaction by the transactional-memory system based upon a comparison of the multiple parameters. | 04-24-2014 |
Patent application number | Description | Published |
20080247887 | PRICING METHOD AND SYSTEM - A pricing method and system. The method includes receiving by a computing system data associated with a business. The data comprises a first list of negotiated pricing rates and associated skills, a second list of requesters, and a third list of suppliers. The computing system, receives business factors data. The computing system determines requester options with respect to the negotiated pricing rates. The requester options are dependent on the business factors data. The computing system determines supplier options with respect to the negotiated pricing rates. The supplier options are dependent on the business factors data. The computing system determines sourcing buyer authorization options with respect to suppliers and the negotiated pricing rates. The computing system generates a pricing report comprising the requester options, the supplier options, the sourcing buyer authorization options, and the business factors data. | 10-09-2008 |
20080306748 | REQUEST MODIFICATION METHOD AND SYSTEM - A modification method and system. The method includes presenting by a computing system to a requester, templates associated with a candidate request. The computing system receives from the requester, first data associated with the candidate request. The computing system generates a request document comprising the first data. The computing system transmits the request document to at least one supplier. The computing system receives from the at least one supplier, a list of candidates. The computing system receives from the requester, a request for modifying the request document. The computing system generates in response to the request for modifying the request document, a modified request document comprising a modified version of the request document. The computing system receives from the requester, approval data approving a transmission of the modified request document. | 12-11-2008 |
20090083094 | RENEWAL METHOD AND SYSTEM - A renewal method and system. The method includes receiving, by a computing system from a requester, a selection of said first candidate from a list of candidates. The computing system retrieves a portion of candidate related data from an original request document for the candidate. The computing system receives from the requester, a selection of at least a one supplier from a list of suppliers. The computing system generates a first renewal request document associated with the first candidate. The first renewal request document includes the portion of the candidate related data from the original request document. The first renewal request document is for first renewing an association between a first company and the first candidate. The computing system transmits the first renewal request document to the at least one supplier. | 03-26-2009 |
20110288955 | SYSTEM FOR PROCESSING A PURCHASE REQUEST FOR GOODS OR SERVICES - An invoice processing system includes a requisition and catalog server (referred to as a Req/Cat Web, or RCW, server), a procurement services system (SAP), and a requester terminal (browser). ReqCat Web allows requesters to input requirements (requisitions) which ReqCat then passes to SAP, which creates purchase orders, sends them to vendors for fulfillment, receives the vendors invoices, and prepares the payments. Commodities may be designated as either receivable or non-receivable, and this designation is stored in ReqCat web and passed to SAP on inbound requisitions. Payments on invoices received for non-receivable items are approved via a positive confirmation process, and payments on invoices received for receivable items are approved via a negative confirmation process. Positive acceptance of an invoice by a requester of commodities triggers automatic generation of a goods received (move) ticket. | 11-24-2011 |