Patent application number | Description | Published |
20110260319 | THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS - Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection. | 10-27-2011 |
20120251029 | OPTICAL WAVEGUIDE STRUCTURE - Embodiments of the invention describe a multi-segment optical waveguide that enables an optical modulator to be low-power and athermal by decreasing the device length needed for a given waveguide length. Embodiments of the invention describe an optical waveguide that is folded onto itself, and thus includes at least two sections. Thus, embodiments of the invention may decrease the device size of a modulator by at least around a factor of two if the device is folded twofold (device size may be further reduced if the modulator is folded threefold, four-fold, five-fold, etc.). | 10-04-2012 |
20120280387 | THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS - Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection. | 11-08-2012 |
20130279845 | FABRICATION OF PLANAR LIGHT-WAVE CIRCUITS (PLCS) FOR OPTICAL I/O - PLC architectures and fabrication techniques for providing electrical and photonic integration of a photonic components with a semiconductor substrate. In the exemplary embodiment, the PLC is to accommodate optical input and/or output (I/O) as well as electrically couple to a microelectronic chip. One or more photonic chip or optical fiber terminal may be coupled to an optical I/O of the PLC. In embodiments the PLC includes a light modulator, photodetector and coupling regions supporting the optical I/O. Spin-on electro-optic polymer (EOP) may be utilized for the modulator while a photodefinable material is employed for a mode expander in the coupling region. | 10-24-2013 |
20130336346 | OPTICAL COUPLING TECHNIQUES AND CONFIGURATIONS BETWEEN DIES - Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an opto-electronic assembly includes a first semiconductor die including a light source to generate light, and a first mode expander structure comprising a first optical material disposed on a surface of the first semiconductor die, the first optical material being optically transparent at a wavelength of the light, and a second semiconductor die including a second mode expander structure comprising a second optical material disposed on a surface of the second semiconductor die, the second material being optically transparent at the wavelength of the light, wherein the second optical material is evanescently coupled with the first optical material to receive the light from the first optical material. Other embodiments may be described and/or claimed. | 12-19-2013 |
20140003765 | WAVEGUIDE INTEGRATION ON LASER FOR ALIGNMENT-TOLERANT ASSEMBLY | 01-02-2014 |
20140086523 | POLING STRUCTURES AND METHODS FOR PHOTONIC DEVICES EMPLOYING ELECTRO-OPTICAL POLYMERS - EOP-based photonic devices employing coplanar electrodes and in-plane poled chromophores and methods of their manufacture. In an individual EOP-based photonic device, enhanced performance is achieved through in-plane poled chromophores having opposing polarities, enabling, for example, a push-pull optical modulator with reduced operational voltage and switching power relative to a conventional MZ modulator. For a plurality of EOP-based photonic devices, enhanced manufacturability is achieved through a sacrificial interconnect enabling concurrent in-plane poling of many EOP regions disposed on a substrate. | 03-27-2014 |
20140203175 | OPTICAL I/O SYSTEM USING PLANAR LIGHT-WAVE INTEGRATED CIRCUIT - Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor. | 07-24-2014 |
20140203400 | METAL-INSULATOR-METAL CAPACITOR FORMATION TECHNIQUES - Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes. | 07-24-2014 |
20140210098 | TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS - Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die. | 07-31-2014 |