Patent application number | Description | Published |
20080202685 | HIGH YIELD PLASMA ETCH PROCESS FOR INTERLAYER DIELECTRICS - A high yield plasma etch process for an interlayer dielectric layer of a semiconductor device is provided, according to an embodiment of which a dielectric layer is etched with a nitrogen-containing plasma. In this way, the formation of polymers on a backside bevel of a substrate is avoided or substantially reduced. Remaining polymer at the backside bevel can be removed in situ by post-etch treatment. Further, a plasma etching device is provided comprising a chamber, a substrate receiving space for receiving a substrate, a plasma generator for generating a plasma in the chamber and a temperature conditioner for conditioning a temperature at an outer circumferential region of the substrate receiving space and thereby minimizing temperature gradients at a bevel of the wafer. | 08-28-2008 |
20080237588 | METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERISTICS DURING FABRICATION OF VIAS OF INTERCONNECT STRUCTURES - By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified. | 10-02-2008 |
20080241756 | ENHANCING LITHOGRAPHY FOR VIAS AND CONTACTS BY USING DOUBLE EXPOSURE BASED ON LINE-LIKE FEATURES - By performing a double exposure process on the basis of bar-like or line-like features, critical via and contact openings may be defined as an intersection, thereby obtaining the desired design dimension on the basis of less critical lithography process windows. Hence, process flexibility may be enhanced while overall throughput may not be substantially negatively affected. | 10-02-2008 |
20080268265 | TECHNIQUE FOR FORMING METAL LINES IN A SEMICONDUCTOR BY ADAPTING THE TEMPERATURE DEPENDENCE OF THE LINE RESISTANCE - By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced. | 10-30-2008 |
20090035936 | SEMICONDUCTOR DEVICE HAVING A GRAIN ORIENTATION LAYER - A manufacturing process of a semiconductor device includes generating a less random grain orientation distribution in metal features of a semiconductor device by employing a grain orientation layer. The less random grain orientation, e.g., a grain orientation distribution which has a higher percentage of grains that have a predetermined grain orientation, may lead to improved reliability of the metal features. The grain orientation layer may be deposited on the metal features wherein the desired grain structure of the metal features may be obtained by a subsequent annealing process, during which the metal feature is in contact with the grain orientation layer. | 02-05-2009 |
20090140244 | SEMICONDUCTOR DEVICE INCLUDING A DIE REGION DESIGNED FOR ALUMINUM-FREE SOLDER BUMP CONNECTION AND A TEST STRUCTURE DESIGNED FOR ALUMINUM-FREE WIRE BONDING - In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon. | 06-04-2009 |
20090140246 | METHOD AND TEST STRUCTURE FOR MONITORING CMP PROCESSES IN METALLIZATION LAYERS OF SEMICONDUCTOR DEVICES - By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by providing test metal lines in the area of the recessed surface topography, the performance of a respective CMP process may be estimated with increased efficiency. | 06-04-2009 |
20090166861 | WIRE BONDING OF ALUMINUM-FREE METALLIZATION LAYERS BY SURFACE CONDITIONING - In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. Moreover, reliable wire bond connections may be obtained by providing a protection layer, such as an oxide layer, after exposing the respective contact metal, such as copper, nickel and the like, thereby providing highly uniform process conditions during the subsequent wire bonding process. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon. | 07-02-2009 |
20090197408 | INCREASING ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE OF A SEMICONDUCTOR DEVICE BY FORMING AN ALLOY - By introducing a metallic species into an exposed surface area of a copper region, the electromigration behavior of this surface area may be significantly enhanced. The incorporation of the metallic species may be accomplished in a highly selective manner so as to not unduly affect dielectric material positioned adjacent to the metal region, thereby essentially avoiding undue increase of leakage currents. | 08-06-2009 |
20090243105 | WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEMICONDUCTOR DEVICE BY PROVIDING A PROTECTIVE LAYER - In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface. | 10-01-2009 |
20090294921 | SEMICONDUCTOR DEVICE COMPRISING METAL LINES WITH A SELECTIVELY FORMED DIELECTRIC CAP LAYER - A dielectric cap layer of a sophisticated metallization system may be provided in a locally restricted manner so as to enable direct contact of the dielectric material of one metallization layer with a low-k dielectric material of a subsequent metallization layer, which may thus provide enhanced adhesion and overall mechanical integrity. | 12-03-2009 |
20090325378 | REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROCESSING BY PERFORMING A DEPOSITION/ETCH CYCLE DURING BARRIER DEPOSITION - A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region. | 12-31-2009 |
20100052137 | ENHANCED WIRE BOND STABILITY ON REACTIVE METAL SURFACES OF A SEMICONDUCTOR DEVICE BY ENCAPSULATION OF THE BOND STRUCTURE - The wire bond structure of sophisticated metallization systems, for instance based on copper, may be provided without a terminal aluminum layer and without any passivation layers for exposed copper surfaces by providing a fill material after the wire bonding process in order to encapsulate at least the sensitive metal surfaces and a portion of the bond wire. Hence, significant cost reduction, reduced cycle times and a reduction of the required process steps may be accomplished independently from the wire bond materials used. Thus, integrated circuits requiring a sophisticated metallization system may be connected by wire bonding to the corresponding package or carrier substrate with a required degree of reliability based on a corresponding fill material for encapsulating at least the sensitive metal surfaces. | 03-04-2010 |
20100052147 | SEMICONDUCTOR DEVICE INCLUDING STRESS RELAXATION GAPS FOR ENHANCING CHIP PACKAGE INTERACTION STABILITY - By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies. | 03-04-2010 |
20100107717 | METHOD AND DEVICE FOR FABRICATING BONDING WIRES ON THE BASIS OF MICROELECTRONIC MANUFACTURING TECHNIQUES - Bonding wires for sophisticated bonding applications may be efficiently formed on the basis of a corresponding template device that may be formed on the basis of semiconductor material, such as silicon, in combination with associated fabrication techniques, such as lithography and etch techniques. Hence, any appropriate diameter and cross-sectional shape may be obtained with a high degree of accuracy and reliability. | 05-06-2010 |
20100109005 | SEMICONDUCTOR DEVICE COMPRISING A DISTRIBUTED INTERCONNECTED SENSOR STRUCTURE FOR DIE INTERNAL MONITORING PURPOSES - In a semiconductor device, electrical measurement data may be obtained with enhanced spatial resolution, for instance from within the entire die region, by providing a distributed sensor structure, each of which may be individually accessed by an appropriate interconnect structure, while nevertheless maintaining the required number of terminals and test signals at a low level. | 05-06-2010 |
20100109131 | REDUCED WAFER WARPAGE IN SEMICONDUCTORS BY STRESS ENGINEERING IN THE METALLIZATION SYSTEM - In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools. | 05-06-2010 |
20100109158 | SEMICONDUCTOR DEVICE INCLUDING A REDUCED STRESS CONFIGURATION FOR METAL PILLARS - In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer that is in tight mechanical contact with the metal pillar. | 05-06-2010 |
20100164098 | SEMICONDUCTOR DEVICE INCLUDING A COST-EFFICIENT CHIP-PACKAGE CONNECTION BASED ON METAL PILLARS - In sophisticated semiconductor devices, a chip-package interconnect structure may be established on the basis of a metal pillar without using a solder bump material in the package. In this case, the complexity of the manufacturing process for forming the wiring system of the package may be significantly reduced, while also providing the possibility of increasing packing density of the pillar structure. | 07-01-2010 |
20100252828 | SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STRUCTURE ALLOWING ELECTRICAL MEASUREMENTS DURING THE FABRICATION PROCESS - A test structure or a circuit element acting temporarily as a test structure may be provided within the die region of sophisticated semiconductor devices, while probe pads may be located in the frame in order to not unduly consume valuable die area. The electrical connection between the test structure and the probe pads may be established by a conductive path including a buried portion, which extends from the die region into the frame below a die seal, thereby maintaining the electrical and mechanical characteristics of the die seal. Hence, enhanced availability of electrical measurement data and superior authenticity of the data may be accomplished, wherein the measurement data may be obtained during the production process. | 10-07-2010 |
20110020958 | METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERISTICS DURING FABRICATION OF VIAS OF INTERCONNECT STRUCTURES - By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified. | 01-27-2011 |
20110024900 | SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM - A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 μm may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region. | 02-03-2011 |
20110124189 | Increasing Electromigration Resistance in an Interconnect Structure of a Semiconductor Device by Forming an Alloy - By introducing a metallic species into an exposed surface area of a copper region, the electromigration behavior of this surface area may be significantly enhanced. The incorporation of the metallic species may be accomplished in a highly selective manner so as to not unduly affect dielectric material positioned adjacent to the metal region, thereby essentially avoiding undue increase of leakage currents. | 05-26-2011 |
20110209548 | ASSESSING METAL STACK INTEGRITY IN SOPHISTICATED SEMICONDUCTOR DEVICES BY MECHANICALLY STRESSING DIE CONTACTS - The metallization system of complex semiconductor devices may be evaluated in terms of mechanical integrity on the basis of a measurement system and measurement procedures in which individual contact elements, such as metal pillars or solder bumps, are mechanically stimulated, while the response of the metallization system, for instance in the form of directly measured forces, is determined in order to quantitatively evaluate mechanical status of the metallization system. In this manner, the complex material systems and the mutual interactions thereof may be efficiently assessed. | 09-01-2011 |
20110244632 | Reduction of Mechanical Stress in Metal Stacks of Sophisticated Semiconductor Devices During Die-Substrate Soldering by an Enhanced Cool Down Regime - In a reflow process for connecting a semiconductor die and a package substrate, the temperature gradient and thus the thermally induced mechanical forces in a sensitive metallization system of the semiconductor die may be reduced during the cooling phase. To this end, one or more heating intervals may be introduced into the cooling phase, thereby efficiently reducing the temperature difference. In other cases, the central region may additionally be cooled by providing appropriate locally restricted mechanisms, such as a locally restricted gas flow and the like. Consequently, desired short overall process times may be obtain without contributing to increased yield losses when processing sophisticated metallization systems on the basis of a lead-free contact regime. | 10-06-2011 |
20110291285 | Semiconductor Device Comprising a Die Seal with Graded Pattern Density - A die seal of a semiconductor device may be provided with a varying pattern density such that a gradient between the die region and the die seal may be reduced. Consequently, for a given width of the die seal, a required mechanical stability may be achieved, while at the same time differences in topography between the die region and the die seal may be reduced, thereby contributing to superior process conditions for sophisticated lithography processes. | 12-01-2011 |
20120009780 | WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEMICONDUCTOR DEVICE BY PROVIDING A PROTECTION LAYER - In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface. | 01-12-2012 |
20120088365 | TECHNIQUE FOR FORMING METAL LINES IN A SEMICONDUCTOR BY ADAPTING THE TEMPERATURE DEPENDENCE OF THE LINE RESISTANCE - By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced. | 04-12-2012 |
20120223445 | SEMICONDUCTOR DEVICE COMPRISING A DIE SEAL HAVING AN INTEGRATED ALIGNMENT MARK - In semiconductor devices, the alignment mark for performing alignment processes of measurement tools and the like may be positioned within the die seal area on the basis of a geometric configuration, which still preserves mechanical integrity of the die seal without compromising the spatial information encoded into the alignment marks. For example, L-shaped alignment marks may be provided at one or more corners of the die seal area. | 09-06-2012 |
20120235285 | PROTECTION OF REACTIVE METAL SURFACES OF SEMICONDUCTOR DEVICES DURING SHIPPING BY PROVIDING AN ADDITIONAL PROTECTION LAYER - When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process. | 09-20-2012 |
20120286397 | Die Seal for Integrated Circuit Device - Disclosed herein is a semiconductor device having a novel stress reduction structures that are employed in an effort to eliminate or at least reduce undesirable cracking or chipping of semiconductor die. In one example, the device includes a die comprising a semiconducting substrate, wherein the die includes a cut surface. The device also includes a first die seal that defines a perimeter, and at least one stress reducing structure, at least a portion of which is positioned between the perimeter defined by the first die seal and the cut surface, wherein the cut surface exposes at least a portion of the stress reducing structure. | 11-15-2012 |
20130234300 | SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM - A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 μm may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region. | 09-12-2013 |
20140035099 | INTEGRATED CIRCUITS WITH METAL-INSULATOR-METAL (MIM) CAPACITORS AND METHODS FOR FABRICATING SAME - Integrated circuits with metal-insulator-metal (MIM) capacitors and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a dielectric material layer overlying a semiconductor substrate. A surface conditioning layer overlies the dielectric material layer. Further, a metal layer is formed directly on the surface conditioning layer. A MIM capacitor is positioned on the metal layer. The MIM capacitor includes a first conductive layer formed directly on the metal layer with a smooth upper surface, an insulator layer formed directly on the smooth upper surface of the first conductive layer, and a second conductive layer formed directly on the insulator layer with a smooth lower surface. | 02-06-2014 |
20150014843 | SEMICONDUCTOR DEVICE WITH IMPROVED METAL PILLAR CONFIGURATION - When forming sophisticated semiconductor devices including metal pillars arranged on contact pads, which may comprise aluminum, device performance and reliability may be improved by avoiding exposure of the contact pad material to the ambient atmosphere, in particular during and between dicing and packaging processes. To this end, the contact pad material may be covered by a protection layer or may be protected by the metal pillars itself, thereby concurrently improving mechanical stress distribution in the device. | 01-15-2015 |