Patent application number | Description | Published |
20080238475 | Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions. | 10-02-2008 |
20090261437 | Two Mask MTJ Integration For STT MRAM - A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization. | 10-22-2009 |
20090273068 | 3-D Integrated Circuit Lateral Heat Dissipation - By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations. | 11-05-2009 |
20090309667 | RING OSCILLATOR USING ANALOG PARALLELISM - An apparatus including a ring oscillator and related methods are disclosed. The ring oscillator includes at least two ring loops. A first ring loop includes a plurality of series coupled delay cells. At least one additional ring loop includes a plurality of series coupled delay cells. The at least one additional ring loop is coupled to the first ring loop by one or more common delay cells shared between the first ring loop and the at least one additional ring loops. | 12-17-2009 |
20090321909 | Active Thermal Control for Stacked IC Devices - Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired. | 12-31-2009 |
20090327983 | Predictive Modeling of Interconnect Modules for Advanced On-Chip Interconnect Technology - A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component. | 12-31-2009 |
20100038801 | Corrosion Control of Stacked Integrated Circuits - A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity. | 02-18-2010 |
20100045630 | Capacitive MEMS-Based Display with Touch Position Sensing - A micro-electro-mechanical systems (MEMS) pixel for display and touch position sensing includes a substrate and a capacitive element. The capacitive element includes one or more pixels having a first conductive platelet above the substrate, and a second conductive platelet above and spaced apart from the first conductive platelet, the two platelets forming the capacitive element. A connection to each platelet provides for applying a voltage, wherein the platelet separation changes according to the applied voltage. A transparent dielectric plate, spaced apart from and positioned opposite the substrate, covers the at least one pixel. A capacitance sensing circuit attached to the connection to each platelet of the pixel senses changes in capacitance not resulting from the applied voltage. | 02-25-2010 |
20100057411 | PREDICTIVE MODELING OF CONTACT AND VIA MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY - A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via. | 03-04-2010 |
20100059869 | Systems and Methods for Enabling ESD Protection on 3-D Stacked Devices - An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry. | 03-11-2010 |
20100102404 | Magnetic Tunnel Junction and Method of Fabrication - In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes applying a dielectric layer to a surface, applying a metal layer to the dielectric layer, and adding a cap layer on the dielectric layer. The method also includes forming a magnetic tunnel junction (MTJ) stack such that an electrode of the MTJ stack is disposed on the metal layer and the cap layer contacts a side portion of the metal layer. An adjustable depth to via may connect a top electrode of the MTJ stack to a top metal. | 04-29-2010 |
20100174661 | Wireless Branding - A device wirelessly broadcasts branding information associated with a consumer product attached to the device. The branding information is sent to a receiver located remotely from the product. | 07-08-2010 |
20100191072 | Button Sensor - A hermetically sealed electronic closure device, or button, includes a self-renewing power source, a sensor for measuring a metric, a memory storing information, a data processing circuit for controlling operations of the device, and a transceiver for sending and receiving information. The device is a standard part of a clothing item that is inconspicuous to a wearer of the clothing item. | 07-29-2010 |
20100193905 | Techniques for Placement of Active and Passive Devices Within a Chip - A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs). | 08-05-2010 |
20100194431 | Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Devices - Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions. | 08-05-2010 |
20100225435 | Magnetic Film Enhanced Inductor - An integrated magnetic film enhanced inductor and a method of forming an integrated magnetic film enhanced inductor are disclosed. The integrated magnetic film enhanced inductor includes an inductor metal having a first portion and a second portion, a top metal or bottom metal coupled to the inductor metal, and an isolation film disposed one of in, on, and adjacent to at least one of the first portion and the second portion of the inductor metal. The isolation film includes a magnetic material, such as a magnetic film. | 09-09-2010 |
20100258887 | Magnetic Tunnel Junction (MTJ) and Methods, and Magnetic Random Access Memory (MRAM) Employing Same - Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided. | 10-14-2010 |
20100295600 | Method and Apparatus for Providing Through Silicon VIA (TSV) Redundancy - An apparatus includes a first die having a first bus, a second die having a second bus stacked on the first die, a plurality of through silicon vias connecting the first bus to the second bus, and first control logic for sending data to identified ones of the plurality of through silicon vias. Also, optionally, second control logic for determining a first set of the plurality of through silicon vias that are nonfunctional, wherein the second control logic is configured to send information to the first control logic identifying the first set of the plurality of through silicon vias or identifying a second set of through silicon vias that are functional. Also a method of sending signals through a plurality of through silicon vias. | 11-25-2010 |
20110050357 | Transformer Signal Coupling for Flip-Chip Integration - Methods and apparatuses for transformer signal coupling for flip-chip circuit assemblies are presented. A device for coupling dies in flip-chip circuit assembly may include a first die associated with a first fabrication process and a first inductor physically coupled to the first die, where the first inductor receives an RF input signal. The device may further include a second die associated with a second fabrication process, and a second inductor physically coupled to the second die, where the second inductor is positioned so the first inductor can inductively couple the RF signal in the second inductor. A method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. | 03-03-2011 |
20110084765 | Three Dimensional Inductor and Transformer - A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip. | 04-14-2011 |
20110254587 | Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Devices - Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions. | 10-20-2011 |
20120001297 | Techniques for Placement of Active and Passive Devices within a Chip - A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs). | 01-05-2012 |
20120040509 | Techniques for Placement of Active and Passive Devices within a Chip - A method for manufacturing a semiconductor device includes fabricating an active layer on a first side of a semiconductor substrate. The method also includes fabricating a metal layer on a second side of the semiconductor substrate. The metal layer includes a passive device embedded within the metal layer. The passive device can electrically couple to the active layer with through vias. | 02-16-2012 |
20120056680 | Three Dimensional Inductor, Transformer and Radio Frequency Amplifier - A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground. | 03-08-2012 |
20120061804 | Systems and Methods for Enabling Esd Protection on 3-D Stacked Devices - An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry. | 03-15-2012 |
20120154333 | CAPACITIVE MEMS-BASED DISPLAY WITH TOUCH POSITION SENSING - A micro-electro-mechanical systems (MEMS) pixel for display and touch position sensing includes a substrate and a capacitive element. The capacitive element includes one or more pixels having a first conductive platelet above the substrate, and a second conductive platelet above and spaced apart from the first conductive platelet, the two platelets forming the capacitive element. A connection to each platelet provides for applying a voltage, wherein the platelet separation changes according to the applied voltage. A transparent dielectric plate, spaced apart from and positioned opposite the substrate, covers the at least one pixel. A capacitance sensing circuit attached to the connection to each platelet of the pixel senses changes in capacitance not resulting from the applied voltage. | 06-21-2012 |
20120274647 | PIEZOELECTRIC RESONATORS AND FABRICATION PROCESSES - This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a sacrificial layer is deposited on an insulating substrate. A lower electrode layer is formed proximate the sacrificial layer. A piezoelectric layer is deposited on the lower electrode layer. An upper electrode layer is formed on the piezoelectric layer. At least a portion of the sacrificial layer is removed to define a cavity such that at least a portion of the lower electrode layer is spaced apart from the insulating substrate. | 11-01-2012 |
20120286886 | Electromechanical Systems Oscillator with Piezoelectric Contour Mode Resonator for Multiple Frequency Generation - Electromechanical systems resonator structures, devices, circuits, and systems are disclosed. In one aspect, an oscillator includes an active component and a passive component connected in a feedback configuration. The passive component includes one or more contour mode resonators (CMR). A CMR includes a piezoelectric layer disposed between a first conductive layer and a second conductive layer. The conductive layers include an input electrode and an output electrode. The passive component is configured to output a first resonant frequency and a second resonant frequency, which is an odd integer harmonic of the first resonant frequency. The active component is configured to output a signal including the first resonant frequency and the second resonant frequency. This output signal can be a substantially square wave signal, which can serve as a clock in various applications. | 11-15-2012 |
20130134533 | MAGNETIC TUNNEL JUNCTION (MTJ) AND METHODS, AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) EMPLOYING SAME - Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided. | 05-30-2013 |
20140306349 | LOW COST INTERPOSER COMPRISING AN OXIDATION LAYER - Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate. | 10-16-2014 |