| Patent application number | Description | Published |
|---|
| 20100077244 | LOW POWER ELECTRONIC SYSTEM ARCHITECTURE USING NON-VOLATILE MAGNETIC MEMORY - A computing system includes at least one functional unit and a magnetic random access memory (MRAM) block coupled to the at least one functional unit. The MRAM block is configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit. | 03-25-2010 |
| 20100308435 | Through Silicon Via With Embedded Decoupling Capacitor - A semiconductor die, having a substrate, includes a through silicon via. The through silicon via includes a decoupling capacitor having a first co-axial conductor, a second co-axial conductor, and a co-axial dielectric separating the first co-axial conductor from the second co-axial conductor. The decoupling capacitor is configured to provide local charge storage for components on the semiconductor die. | 12-09-2010 |
| 20110035529 | Partitioning a Crossbar Interconnect in a Multi-Channel Memory System - A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar interconnect. The method includes partitioning the crossbar interconnect into a plurality of partitions comprising at least a first partition corresponding to the first set of masters and a second partition corresponding to the second set of masters. The method also includes allocating a first set of buffer areas within the multi-channel memory. The first set of buffer areas correspond to the first set of masters. The method further includes allocating a second set of buffer areas within the multi-channel memory. The second set of buffers correspond to the second set of masters. | 02-10-2011 |
| 20110087846 | Accessing a Multi-Channel Memory System Having Non-Uniform Page Sizes - A method includes predicting a memory access pattern of each master of a plurality of masters. The plurality of masters can access a multi-channel memory via a crossbar interconnect, where the multi-channel memory has a plurality of banks The method includes identifying a page size associated with each bank of the plurality of banks The method also includes assigning at least one bank of the plurality of banks to each master of the plurality of masters based on the memory access pattern of each master. | 04-14-2011 |
| 20110193212 | Systems and Methods Providing Arrangements of Vias - A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values. | 08-11-2011 |
| 20110233718 | Heterogeneous Technology Integration - A heterogeneous integrated circuit having at least one tier made of multiple technologies and a method of making the heterogeneous integrated circuit. The heterogeneous integrated circuit includes a package substrate, a first die of a first technology, and a second die of a second technology, where the two dies are located in the same tier. One die can surround the other die. The heterogeneous integrated circuit can also include a wire-bond and/or horizontal micro-bump coupling the two dies. The heterogeneous integrated circuit can also include a wire bond or vertical micro-bump coupling one of the dies to the package substrate. The vertical micro-bump coupling can include a through-via. The two technologies can be any of various technologies including CMOS, glass, sapphire and quartz. One die can also be adjacent to the other die on the same tier and the two dies coupled using a horizontal micro-bump. | 09-29-2011 |
| 20110234357 | Three Dimensional Inductor and Transformer Design Methodology of Glass Technology - An inductor or transformer for use in integrated circuit devices that includes a high-resistivity substrate. The inductor includes a plurality of conductive traces around the substrate forming a continuous conductive path from a first to a second port. The conductive path can be solenoid-shaped. Some of the conductive traces can be formed during back-end-of-line processing or backside plating of an integrated circuit die. The transformer includes a first inductor with input and output ports, and a first continuous conductive path therebetween; and a second inductor with input and output ports, and a second continuous conductive path therebetween. The second inductor is independent of and electromagnetically coupled to the first inductor. The first and second conductive paths can be solenoid-shaped. The first conductive path can be interleaved with the second conductive path. | 09-29-2011 |
| 20110273926 | Method and Apparatus of Probabilistic Programming Multi-Level Memory in Cluster States Of Bi-Stable Elements - A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data. | 11-10-2011 |
