| Patent application number | Description | Published |
|---|
| 20090081563 | Integrated Circuits and Methods of Design and Manufacture Thereof - Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features. | 03-26-2009 |
| 20090081579 | FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME - Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm | 03-26-2009 |
| 20090081585 | FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME - Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm | 03-26-2009 |
| 20090081597 | FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME - Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm | 03-26-2009 |
| 20090081598 | FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME - Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm | 03-26-2009 |
| 20090104566 | Process of multiple exposures with spin castable film - Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures. | 04-23-2009 |
| 20090203200 | GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH - A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation. | 08-13-2009 |
| 20090233236 | METHOD FOR FABRICATING SELF-ALIGNED NANOSTRUCTURE USING SELF-ASSEMBLY BLOCK COPOLYMERS, AND STRUCTURES FABRICATED THEREFROM - In one embodiment, the present invention provides a method for patterning a surface that includes forming a block copolymer atop a heterogeneous reflectivity surface, wherein the block copolymer is segregated into first and second units; applying a radiation to the first units and second units, wherein the heterogeneous reflectivity surface produces an exposed portion of the first units and the second units; and applying a development cycle to selectively remove at least one of the exposed first and second units of the segregated copolymer film to provide a pattern. | 09-17-2009 |
| 20090246958 | METHOD FOR REMOVING RESIDUES FROM A PATTERNED SUBSTRATE - The present invention relates to a method for removing residues from open areas of a patterned substrate involving the steps of providing a layer of a developable anti-reflective coating (DBARC) over a substrate; providing a layer of a photoresist over said DBARC layer; pattern-wise exposing said photoresist layer and said DBARC layer to a radiation; developing said photoresist layer and said DBARC layer with a first developer to form patterned structures in said photoresist and DBARC layers; depositing a layer of a developer soluble material over said patterned structures; and removing said developer soluble material with a second developer. | 10-01-2009 |
| 20090311490 | CHEMICAL TRIM OF PHOTORESIST LINES BY MEANS OF A TUNED OVERCOAT MATERIAL - A new lithographic process comprises reducing the linewidth of an image while maintaining the lithographic process window, and using this process to fabricate pitch split structures comprising nm order (e.g., about 22 nm) node semiconductor devices. The process comprises applying a lithographic resist layer on a surface of a substrate and patterning and developing the lithographic resist layer to form a nm order node image having an initial line width. Overcoating the nm order node image with an acidic polymer produces an acidic polymer coated image. Heating the acidic polymer coated image gives a heat treated coating on the image, the heating being conducted at a temperature and for a time sufficient to reduce the initial linewidth to a subsequent narrowed linewidth. Developing the heated treated coating removes it from the image resulting in a free-standing trimmed lithographic feature on the substrate. Optionally repeating the foregoing steps further reduces the linewidth of the narrowed line. The invention also comprises a product produced by this process. | 12-17-2009 |
| 20110045407 | Functionalized Carbosilane Polymers and Photoresist Compositions Containing the Same - Linear or branched functionalized polycarbosilanes having an absorbance less than 3.0 μm | 02-24-2011 |
| 20110147984 | METHODS OF DIRECTED SELF-ASSEMBLY, AND LAYERED STRUCTURES FORMED THEREFROM - A method of forming a layered structure comprising a self-assembled material comprises: disposing a non-crosslinking photoresist layer on a substrate; pattern-wise exposing the photoresist layer to first radiation; optionally heating the exposed photoresist layer; developing the exposed photoresist layer in a first development process with an aqueous alkaline developer, forming an initial patterned photoresist layer; treating the initial patterned photoresist layer photochemically, thermally and/or chemically, thereby forming a treated patterned photoresist layer comprising non-crosslinked treated photoresist disposed on a first substrate surface; casting a solution of an orientation control material in a first solvent on the treated patterned photoresist layer, and removing the first solvent, forming an orientation control layer; heating the orientation control layer to effectively bind a portion of the orientation control material to a second substrate surface; removing at least a portion of the treated photoresist and, optionally, any non-bound orientation control material in a second development process, thereby forming a pre-pattern for self-assembly; optionally heating the pre-pattern; casting a solution of a material capable of self-assembly dissolved in a second solvent on the pre-pattern and removing the second solvent; and allowing the casted material to self-assemble with optional heating and/or annealing, thereby forming the layered structure comprising the self-assembled material. | 06-23-2011 |
