| Patent application number | Description | Published |
|---|
| 20090047799 | GATE OXIDE LEAKAGE REDUCTION - A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation process after the first anneal process, subjecting the gate oxide layer to a second anneal process after the second nitridation process, and forming a gate electrode over the gate oxide. | 02-19-2009 |
| 20100048011 | METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 02-25-2010 |
| 20100068875 | DOUBLE TREATMENT ON HARD MASK FOR GATE N/P PATTERNING - The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region, forming first and second gate stacks over the first and second regions, respectively, the first and second gate stacks each including a dummy gate electrode, removing the dummy gate electrodes from the first and second gate stacks, respectively, thereby forming trenches, forming a metal layer to partially fill the trenches, forming an oxide layer over the metal layer filling a remaining portion of the trenches, applying a first treatment to the oxide layer, forming a patterned photoresist layer on the oxide layer overlying the first region, applying a second treatment to the oxide layer overlying the second region, etching the oxide layer overlying the second region, etching the first metal layer overlying the second region, removing the patterned photoresist layer, and removing the oxide layer overlying the first region. | 03-18-2010 |
| 20100112811 | METHOD FOR PATTERNING A METAL GATE - The present disclosure provides a method for fabricating a semiconductor device. The method includes forming first, second, third, and fourth gate structures on a semiconductor substrate, each gate structure having a dummy gate, removing the dummy gate from the first, second, third, and fourth gate structures, thereby forming first, second, third, and fourth trenches, respectively, forming a metal layer to partially fill in the first, second, third, and fourth trenches, forming a first photoresist layer over the first, second, and third trenches, etching a portion of the metal layer in the fourth trench, removing the first photoresist layer, forming a second photoresist layer over the second and third trenches, etching the metal layer in the first trench and the remaining portion of the metal layer in the fourth trench, and removing the second photoresist layer. | 05-06-2010 |
| 20100124818 | FABRICATING HIGH-K/METAL GATE DEVICES IN A GATE LAST PROCESS - The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches. | 05-20-2010 |
| 20100124823 | NOVEL METHOD FOR REMOVING DUMMY POLY IN A GATE LAST PROCESS - A method is provided for fabricating a semiconductor device. The method includes removing a silicon material from a gate structure located on a substrate through a cycle including: etching the silicon material to remove a portion thereof, where the substrate is spun at a spin rate, applying a cleaning agent to the substrate, and drying the substrate; and repeating the cycle, where a subsequent cycle includes a subsequent spin rate for spinning the substrate during the etching and where the subsequent spin rate does not exceed the spin rate of the previous cycle. | 05-20-2010 |
| 20110081774 | METHODS FOR A GATE REPLACEMENT PROCESS - A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process. | 04-07-2011 |
| 20110143510 | METHOD OF CONTROLLING GATE THICKNESS IN FORMING FINFET DEVICES - A method of forming a FinFET device is provided. In one embodiment, a fin is formed on a substrate. A gate structure is formed over the fin, the gate structure having a dielectric layer and a conformal first polysilicon layer formed above the dielectric layer. An etch stop layer is formed above the first polysilicon layer and thereafter a second polysilicon layer is formed above the etch stop layer. The second polysilicon layer and the etch stop layer are removed. A metal layer is formed above the first polysilicon layer. The first polysilicon layer is reacted with the metal layer to silicide the first polysilicon layer. Any un-reacted metal layer is thereafter removed and source and drain regions are formed on opposite sides of the fin. | 06-16-2011 |
| 20110143529 | METHOD OF FABRICATING HIGH-K/METAL GATE DEVICE - The present disclosure provides a method that includes providing a semiconductor substrate; forming a gate structure over the semiconductor substrate, first gate structure including a dummy dielectric and a dummy gate disposed over the dummy dielectric; removing the dummy gate and the dummy dielectric from the gate structure thereby forming a trench; forming a high-k dielectric layer partially filling the trench; forming a barrier layer over the high-k dielectric layer partially filling the trench; forming an capping layer over the barrier layer partially filling the trench; performing an annealing process; removing the capping layer; forming a metal layer over the barrier layer filling in a remainder of the trench; and performing a chemical mechanical polishing (CMP) to remove the various layers outside the trench. | 06-16-2011 |
