| Patent application number | Description | Published |
|---|
| 20090017178 | Method for Reducing the Oil Content of Potato Chips - A method is disclosed which reduces the oil content of a potato chip. The method teaches that a steeper, faster temperature drop upon initial introduction of the potato slice to the fryer, followed by a longer period of exposure to lower temperatures before increasing to standard frying temperatures, reduces oil content of a potato chip. The invention further discloses a pre-treatment method which involves submerging the potatoes in a hot water bath which results in decreased oil content. Additionally, the invention discloses a post-treatment method involving subjecting the potato chip to superheated steam that further reduces oil content. The two pre and post-treatment methods, combined with the primary temperature scheme method for reducing oil content, yield a potato chip with significantly reduced oil content. | 01-15-2009 |
| 20110281005 | METHOD FOR REDUCING THE OIL CONTENT OF POTATO CHIPS - A method is disclosed which reduces the oil content of a potato chip. The method teaches that a steeper, faster temperature drop upon initial introduction of the potato slice to the fryer, followed by a longer period of exposure to lower temperatures before increasing to standard frying temperatures, reduces oil content of a potato chip. The invention further discloses a pre-treatment method which involves submerging the potatoes in a hot water bath which results in decreased oil content. Additionally, the invention discloses a post-treatment method involving subjecting the potato chip to superheated steam that further reduces oil content. The two pre and post-treatment methods, combined with the primary temperature scheme method for reducing oil content, yield a potato chip with significantly reduced oil content. | 11-17-2011 |
| Patent application number | Description | Published |
|---|
| 20080197497 | BARRIER FOR USE IN 3-D INTEGRATION OF CIRCUITS - A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad. | 08-21-2008 |
| 20080299759 | Method to form a via - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 12-04-2008 |
| 20080299762 | Method for forming interconnects for 3-D applications - A method for forming an interconnect, comprising (a) providing a substrate ( | 12-04-2008 |
| 20090170246 | FORMING A 3-D SEMICONDUCTOR DIE STRUCTURE WITH AN INTERMETALLIC FORMATION - A method for forming a semiconductor structure includes forming a first contact pad on a first die, wherein the first contact pad comprises a first metal element, forming a metal over the first contact pad, wherein the metal comprises a second metal element, and the second metal element is different from the first metal element. The method further includes rapidly reflowing a portion of the metal to form a thin intermetallic layer. The method further includes attaching the first contact pad of the first die to a second contact pad of a second die, wherein attaching comprises heating the first contact pad and the second contact pad to reflow the metal to form an intermetallic layer such that substantially all of the metal formed over the first contact pad is used as part of the intermetallic layer. | 07-02-2009 |
| 20090176366 | MICROPAD FORMATION FOR A SEMICONDUCTOR - A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips. | 07-09-2009 |
| 20090218567 | CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MAKING THE SAME - A method for making a semiconductor device ( | 09-03-2009 |
| 20110151663 | METHOD TO FORM A VIA - A method for forming a via, comprising (a) providing a structure comprising a mask ( | 06-23-2011 |
| 20110198751 | BOND PAD WITH MULTIPLE LAYER OVER PAD METALLIZATION AND METHOD OF FORMATION - A semiconductor device structure has a semiconductor die that has a bond pad with a passivation layer surrounding a portion of the bond pad. A nickel layer, which is deposited, is on the inner portion. A space is between a sidewall of the nickel layer and the passivation layer and extends to the bond pad. A palladium layer is over the nickel layer and fills the space. The space is initially quite small but is widened by an isotropic etch so that when the palladium layer is deposited, the space is sufficiently large so that the deposition of palladium is able to fill the space. Filling the space results in a structure in which the palladium contacts the nickel layer, the passivation layer and the bond pad. | 08-18-2011 |
