| Patent application number | Description | Published |
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| 20090246504 | Polishing Pad With Controlled Void Formation - A chemical-mechanical planarization polishing pad is provided comprising a network of elements dispersed within a polymer, a plurality of voids formed in the pad and at least a portion of said network of elements is connected to at least a portion of the voids. A method of forming the pad is also disclosed, which comprises providing a composition, the composition comprising a network of elements and at least one of a polymer or a reactive prepolymer, introducing a gas to the composition and using the gas to produce a plurality of voids in the composition. A method of forming voids is also disclosed, which relies upon the application of a force to the network of elements within the polymer or reactive polymer, followed by removal of the force and void formation. | 10-01-2009 |
| 20100221983 | MULTI-LAYERED CHEMICAL-MECHANICAL PLANARIZATION PAD - The present disclosure relates to a chemical mechanical planarization pad and a method of making and using a chemical mechanical planarization pad. The chemical mechanical planarization pad may include a first component including a water soluble composition and water insoluble composition exhibiting a solubility in water of less than that of the water soluble composition, wherein at least one of the water soluble and water insoluble compositions of the first component is formed of fibers. The chemical mechanical planarization pad may also include a second component, wherein the first component is present as a discrete phase in a continuous of the second component. | 09-02-2010 |
| 20100221985 | CHEMICAL-MECHANICAL PLANARIZATION PAD INCLUDING PATTERNED STRUCTURAL DOMAINS - An aspect of the present disclosure relates to a chemical mechanical planarization pad including a first domain and a second continuous domain wherein the first domain includes discrete elements regularly spaced within the second continuous domain. The pad may be formed by forming a plurality of openings for a first domain within a second continuous domain of the pad, wherein the openings are regularly spaced within the second domain, and forming the first domain within the plurality of openings in second continuous domain. In addition, the pad may be used in polishing a substrate with a polishing slurry. | 09-02-2010 |
| Patent application number | Description | Published |
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| 20090081973 | Multi-slot power control for wireless transmission - Methods and apparatus are provided for controlling transmitted power in a wireless system. The method includes generating information to be transmitted as a series of signal bursts, with a time interval between successive signal bursts, controlling individually a power level of each of said signal bursts with a power control signal to provide output signal bursts to be transmitted, and asserting a new power value of the power control signal during the time interval preceding each signal burst. The wireless system can be a TDSCDMA wireless system, and the signal bursts can be uplink signal bursts. | 03-26-2009 |
| 20090161647 | TD-SCDMA UPLINK PROCESSING - A wireless system has an uplink chip rate processing architecture in which at least two groups of registers are provided, each group of register storing a set of time slot configuration parameters. A storage stores a sequence of time slot configuration set identifiers each identifying one of the groups of registers, each identifier corresponding to a time slot. A chip rate processing unit processes a stream of data over a plurality of time slots in which at each of the time slots, and the chip rate processing unit is configured according to the set of time slot configuration parameters stored in the group of register associated with the time slot configuration set identifier corresponding to the time slot. | 06-25-2009 |
| 20090161648 | TD-SCDMA UPLINK PROCESSING - A wireless device has a BRP-CRP interface that includes a dual-port frame memory having a first access port and a second access port in which data can be written to the dual-port frame memory through the first access port at the same time that data is read from the dual-port frame memory through the second access port. A bit rate processor performs bit rate processing on input data and writes data resulting from the bit rate processing to the dual-port frame memory through the first access port. A chip rate processor reads data from the dual-port frame memory through the second access port and performs chip rate processing on the data read from the dual-port frame memory. A data processor executes a software application that writes data to the dual-port frame memory through the first access port and reads data from the dual-port frame memory through the second access port. | 06-25-2009 |
| 20090161745 | Parameter Estimation for Modulated Signals - A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation. | 06-25-2009 |
| 20090165019 | Data Flow Control - A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots. | 06-25-2009 |
| 20090175205 | Multi-mode Bit Rate Processor - An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output. | 07-09-2009 |
