Patent application number | Description | Published |
20080296717 | Packages and assemblies including lidded chips - A lidded chip is provided which includes a chip having a major surface and a plurality of first chip contacts exposed at the major surface. A lid overlies the major surface. A chip carrier is disposed between the chip and the lid, the chip carrier having an inner surface confronting the major surface and an outer surface confronting the lid. A plurality of first carrier contacts of the chip carrier are conductively connected to the first chip contacts. A plurality of second carrier contacts extend upwardly at least partially through the openings in the lid. | 12-04-2008 |
20080296748 | Transmission line stacking - A microelectronic unit has a structure including a microelectronic element such as a semiconductor chip with a first contact disposed remote from the periphery of the structure. The unit further includes first and second redistribution conductive pads disposed near a periphery of the structure and a conductive path incorporating first and second conductors extending toward the first contact, these conductors being connected to one another adjacent the first contact. The conductive path is connected to the first contact, and can provide signal routing from the periphery of the unit to the contact without the need for long stubs. A package may include a plurality of such units, which may be stacked on one another with the redistribution conductive pads of the various units connected to one another. | 12-04-2008 |
20090071000 | Formation of circuitry with modification of feature height - A connection component for mounting a chip or other microelectronic element is formed from a starting unit including posts projecting from a dielectric element by crushing or otherwise reducing the height of at least some of the posts. | 03-19-2009 |
20090104736 | Stacked Packaging Improvements - A plurality of microelectronic assemblies ( | 04-23-2009 |
20100258956 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package. | 10-14-2010 |
Patent application number | Description | Published |
20120138343 | THREE DIMENSIONAL INTERPOSER DEVICE, CHIP PACKAGE AND PROBE CARD CONTACTOR - A three-dimensional grid array interposer includes first and second arrays of electrical terminals arranged in grid-like patterns having grid pitches of (X1,Y1) and (X2,Y2), where each electrical terminal of the first array corresponds to an electrical terminal of the second array, forming a corresponding pair of electrical terminals. The interposer also includes a plurality of stacked substrates, each substrate having a first surface, a second surface, a first edge, and a second edge, with each substrate having a row of electrical terminals of the first array along the first surface at the first edge and a row of electrical terminals of the second array along the first surface at its second edge, with a trace running along the first surface between each electrical terminal of each corresponding pair of electrical terminals. Spacers can be used to provide desired space transformation. | 06-07-2012 |
20130126921 | INVERTED OPTICAL DEVICE - Inverted optical device. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. A flip wafer is attached to the plurality of light emitting diodes, away from the carrier wafer and the carrier wafer is removed. The plurality of light emitting diodes may be singulated to form individual light emitting diode devices. | 05-23-2013 |
20130127364 | FRONT FACING PIGGYBACK WAFER ASSEMBLY - Front facing piggyback wafer assembly. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. The plurality of integrated circuit devices are singulated to form individual integrated circuit devices. The carrier wafer may be processed to form integrated circuit structures prior to the attaching. | 05-23-2013 |
20130214296 | HEAT SPREADING SUBSTRATE WITH EMBEDDED INTERCONNECTS - Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another. | 08-22-2013 |
20140008676 | OPTICAL ENHANCEMENT OF LIGHT EMITTING DEVICES - Optical enhancement of light emitting devices. In accordance with an embodiment of the present invention, an apparatus includes an optical enhancement layer comprising nanoparticles. Each of the nanoparticles includes an electrically conductive core surrounded by an electrically insulating shell. The optical enhancement layer is disposed on a top semiconductor layer in a preferred path of optical emission of a light emitting device. The nanoparticles may enhance the light emission of the light emitting device due to emitter-surface plasmon coupling. | 01-09-2014 |