Patent application number | Description | Published |
20100103998 | DECISION FEEDBACK EQUALIZATION SCHEME WITH MINIMUM CORRECTION DELAY - A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer. | 04-29-2010 |
20100104000 | ENHANCEMENT OF TRANSITION REGION EQUALIZATION IN A DECISION FEEDBACK EQUALIZER - A decision feedback equalizer includes an input path for receiving a bitstream with inter-symbol interference, and a feedback signal path is coupled to the input path for correcting a sampled value of an incoming bit of the bitstream based on inter-symbol interference of a preceding bit. The feedback signal path includes a controllable delay circuit for receiving the preceding bit. A feedback path controller is coupled to the controllable delay circuit to regulate a delay introduced to the preceding bit. The delay is a function of an accumulated value of data of early-late events of a sampling instant of the bitstream for different data pulse patterns. | 04-29-2010 |
20110080218 | INTEGRATED CIRCUIT OF AN INTEGRATOR WITH ENHANCED STABILITY AND RELATED STABILIZATION METHOD - An integrated circuit integrator includes a first transconductance amplifier having a gain adjustable based upon a first control signal, and receives, as an input, a signal to be filtered, and generates, as an output, a corresponding amplified signal. The first transconductance amplifier includes an R-C output circuit to filter components from the amplified signal, and an output resistance being adjustable based upon a second control signal. A second transconductance amplifier is matched with the first transconductance amplifier, and has a gain adjustable based upon the first control signal, and a matched output resistance adjustable based upon the second control signal. A circuit is configured to force a reference current through the matched output resistance. An error correction circuit is coupled to the second transconductance amplifier and is configured to generate the second control signal so as to keep constant a voltage on an output of the second transconductance amplifier. | 04-07-2011 |
20120286870 | INTEGRATED CIRCUIT OF AN INTEGRATOR WITH ENHANCED STABILITY AND RELATED STABILIZATION METHOD - An integrated circuit integrator includes a first transconductance amplifier having a gain adjustable based upon a first control signal, and receives, as an input, a signal to be filtered, and generates, as an output, a corresponding amplified signal. The first transconductance amplifier includes an R-C output circuit to filter components from the amplified signal, and an output resistance being adjustable based upon a second control signal. A second transconductance amplifier is matched with the first transconductance amplifier, and has a gain adjustable based upon the first control signal, and a matched output resistance adjustable based upon the second control signal. A circuit is configured to force a reference current through the matched output resistance. An error correction circuit is coupled to the second transconductance amplifier and is configured to generate the second control signal so as to keep constant a voltage on an output of the second transconductance amplifier. | 11-15-2012 |
20130156087 | A DECISION FEEDBACK EQUALIZATION SCHEME WITH MINIMUM CORRECTION DELAY - A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer. | 06-20-2013 |
20130308893 | INTEGRATED DRIVER AND RELATED METHOD - A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd | 11-21-2013 |
20140361815 | FREQUENCY DOUBLER AND RELATED METHOD OF GENERATING AN OSCILLATING VOLTAGE - A frequency doubling device suitable to generate an output terminal voltage oscillating at a differential frequency double the frequency of the input differential voltage, includes a first differential pair of P-type transistors and a second differential pair of N-type transistors controlled by the differential input voltage, as well as an LC oscillator including a LC resonant dipole through which the absorbed current is forced by two differential pairs of transistors. | 12-11-2014 |
20150301362 | INTEGRATED DRIVER AND RELATED METHOD - A driver circuit may include a first node, and a first circuit to generate on the first node an inverted replica of an input signal during driver switching between a first supply voltage and a first reference voltage, the inverted replica having a threshold voltage value based upon a second reference voltage greater than the first supply voltage. The driver circuit may include a cascode stage to be controlled by the second reference voltage and to be coupled between a second supply voltage and the first node, a delay circuit to generate a delayed replica of the input signal, an amplifier, and a switching network to couple the control terminal of the active load transistor to one of the first reference voltage and the first node based upon the input signal. | 10-22-2015 |