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Masazumi Amagai
Masazumi Amagai, Tsukuba-City JP
| Patent application number | Description | Published |
|---|---|---|
| 20110024899 | SUBSTRATE STRUCTURE FOR CAVITY PACKAGE - Various embodiments provide semiconductor devices having cavity substrate structures for package-on-package assembly and methods for their fabrication. In one embodiment, the cavity substrate structure can include at least one top interconnect via formed within a top substrate. The top substrate can be disposed over a base substrate having at least one base interconnect via that is not aligned with the top interconnect via. Semiconductor dies can be assembled in an open cavity of the top substrate and attached to a base center portion of the base substrate of the cavity substrate structure. A top semiconductor package can be mounted over the top substrate of the cavity substrate structure. | 02-03-2011 |
Masazumi Amagai, Tsukuba-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100032840 | Semiconductor Device with an Improved Solder Joint - A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles. | 02-11-2010 |
| 20100171226 | IC HAVING TSV ARRAYS WITH REDUCED TSV INDUCED STRESS - An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively. | 07-08-2010 |
| 20100291734 | Semiconductor Device with an Improved Solder Joint - A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles. | 11-18-2010 |
Masazumi Amagai, Ibaraki-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20100144098 | Method for Fabricating Flip-Attached and Underfilled Semiconductor Devices - A semiconductor device ( | 06-10-2010 |
Masazumi Amagai, Ibaraki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100025837 | COMPOSITE SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND SPACER SHEET USED IN THE SAME, AND METHOD FOR MANUFACTURING COMPOSITE SEMICONDUCTOR DEVICE - The present invention relates to a complex type semiconductor device formed by laminating plural semiconductor packages, wherein it comprises: | 02-04-2010 |
| 20100090323 | COMPOSITE TYPE SEMICONDUCTOR DEVICE SPACER SHEET, SEMICONDUCTOR PACKAGE USING THE SAME, COMPOSITE TYPE SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND COMPOSITE TYPE SEMICONDUCTOR DEVICE - The present invention provides a spacer sheet for a complex type semiconductor device provided between the semiconductor packages of a complex type semiconductor device formed by laminating plural semiconductor packages, comprising through holes of an array corresponding to electrodes which can be provided onto a substrate of one semiconductor package and which are formed in order to connect and wire one semiconductor package with the other semiconductor package and a space part corresponding to a principal part of the above one semiconductor package mounted on the substrate or a principal part of the other semiconductor package opposed to the substrate and a production process for a complex type semiconductor device in which the above spacer sheet is used. It further provides a wiring and connecting method by using a spacer sheet which satisfies securing of a distance between connection terminals and a narrow pitch at the same time in a POP type semiconductor package and a complex type semiconductor device of a POP type which is increased in a packaging density by the above wiring and connecting method. | 04-15-2010 |
Masazumi Amagai, Tsujyba-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090176336 | Method of Manufacturing a Semiconductor Device - The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements | 07-09-2009 |