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Masayuki Tanaka
Masayuki Tanaka, Yamaguchi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090036453 | Pyrrolopyridazinone Compound - The present invention discloses a pyrrolopyridazinone compound represented by the formula (1): | 02-05-2009 |
| 20110054172 | PYRIDYLAMINOACETIC ACID COMPOUND - The present invention provides a novel pyridylaminoacetic acid compound represented by the following formula (1): | 03-03-2011 |
Masayuki Tanaka, Yokohama JP
| Patent application number | Description | Published |
|---|---|---|
| 20090152618 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film, an intermediate insulating film formed on the first silicon oxide film and having a relative permittivity of not less than 7, and a second silicon oxide film formed on the intermediate insulating film. A charge trap layer is formed at least in either first or second silicon oxide film or a boundary between the first silicon oxide film and the intermediate insulating film or a boundary between the second silicon oxide film and the intermediate insulating film. | 06-18-2009 |
| 20090189213 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region, a gate electrode of a memory cell transistor formed by depositing an electrical charge storage layer formed on an upper surface of the gate insulating film, a second gate insulating film and a control gate insulating film sequentially, an element isolation insulating film buried in each trench and formed from a coating type oxide film, and an insulating film formed inside each trench on a boundary between the semiconductor substrate and the element isolation insulating film, the insulating film containing nontransition metal atoms and having a film thickness not more than 5 Å. | 07-30-2009 |
| 20090242969 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device including a semiconductor substrate including an upper surface having a plurality of trenches formed into the upper surface; a plurality of element isolation insulating films filled in each of the trenches so as to protrude upward from the upper surface of the semiconductor substrate, the element isolation insulating films containing an oxide material; a tunnel insulating film formed on the semiconductor substrate situated between the element isolation insulating films; a charge storing layer comprising a first nitride film and being formed on the tunnel insulating film; a block film formed across an upper surface of the charge storing layer and an upper surface of the element isolation insulating film to prevent charge transfer; a gate electrode formed on the block film; and a barrier layer containing a second nitride film formed between the element isolation insulating film and the block film. | 10-01-2009 |
| 20100102377 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulating layer formed on the semiconductor substrate, a plurality of charge storage layers formed on the first insulating layer, a plurality of element isolation insulating films formed between the charge storage layers respectively, a second insulating layer formed on the charge storage layers and the element isolation insulating films, the second insulating layer including a stacked structure of a first silicon nitride film, a first silicon oxide film, an intermediate insulating film having a relative dielectric constant of not less than 7 and a second silicon oxide film, and a control electrode formed on the second insulating layer. The first silicon nitride film has a nitrogen concentration of not less than 21×10 | 04-29-2010 |
| 20100308393 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate having an active region isolated by an element isolation insulating film; a floating gate electrode film formed on a gate insulating film residing on the active region; an interelectrode insulating film formed above an upper surface of the element isolation insulating film and an upper surface and sidewalls of the floating gate electrode film, the interelectrode insulating film being configured by multiple film layers including a high dielectric film having a dielectric constant equal to or greater than a silicon nitride film; a control gate electrode film formed on the interelectrode insulating film; and a silicon oxide film formed between the upper surface of the floating gate electrode film and the interelectrode insulating film; wherein the high dielectric film of the interelectrode insulating film is placed in direct contact with the sidewalls of the floating gate electrode film. | 12-09-2010 |
| 20110133267 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a charge accumulation layer, an intermediate insulating film and a conductive layer sequentially on the gate insulating film, forming an electrode isolating trench in the conductive layer, the intermediate insulating film and the charge accumulation layer, forming a nitride film on upper and side surfaces of the conductive layer, side surfaces of the intermediate insulating film, side surfaces of the charge accumulation layer and an upper surface of the gate insulating film, removing the nitride film formed on the upper surface of the gate insulating film, and filling the electrode isolating trench with an insulating film. | 06-09-2011 |
| 20110204433 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device is disclosed. The nonvolatile semiconductor storage device includes a semiconductor substrate including a surface layer; an element isolation insulating film isolating the surface layer of the semiconductor device into a plurality of active regions; a first gate insulating film formed above the active regions; a charge storing layer formed above the first gate insulating film and including a silicon layer containing an upper layer selectively doped with carbon; a second gate insulating film formed above the charge storing layer; and a control gate electrode formed above the second gate insulating film. | 08-25-2011 |
| 20110298039 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH CHARGE STORAGE LAYER IN MEMORY CELL - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7. | 12-08-2011 |
| 20110312155 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a first insulating layer, charge storage layers, element isolation insulating films, and a second insulating layer formed on the charge storage layers and the element isolation insulating films and including a stacked structure of a first silicon nitride film, first silicon oxide film, intermediate insulating film and second silicon oxide film. The first silicon nitride film has a nitrogen concentration of not less than 21×10 | 12-22-2011 |
Masayuki Tanaka, Aichi-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20100286883 | VEHICLE DRIVING APPARATUS AND CONTROL METHOD FOR SAME - When the condition for starting an engine ( | 11-11-2010 |
Masayuki Tanaka, Toyota-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090093335 | TRANSMISSION AND POWER TRANSMITTING SYSTEM - A transmission includes: a plurality of rotating elements interposed between a driving source and an output portion; a rotating member that rotatably supports one of the rotating elements and is formed at a radially outer portion thereof with a plurality of recesses or protrusions; a support member having a surface, that is facing the rotating member, and a plurality of protrusions or recesses that are formed in a radially inner portion thereof and engage with the recesses or protrusions of the rotating member, the rotating member being mounted in the support member such that the rotating member is not able to rotate; and a friction producing mechanism that is provided between the rotating member and the above-indicated surface of the support member and is arranged to produce a frictional force between the rotating member and the surface of the support member. | 04-09-2009 |
| 20100262322 | CONTROL APPARATUS OF VEHICLE DRIVE APPARATUS AND PLUG-IN HYBRID VEHICLE - A hybrid control controller stores vehicle speed influence values that have been set according to vehicle speeds, a first threshold value of a sum value of the vehicle speed influence values, a second threshold value lower than the first threshold value, and an engine start reference vehicle speed, and during EV running, sums the vehicle speed influence values from moment to moment. The hybrid control controller starts the engine in a case where the sum value is no less than the first threshold value, and in a case where the sum value is no less than the second threshold value and the vehicle speed is no more than an engine start reference vehicle speed. | 10-14-2010 |
Masayuki Tanaka, Osaka JP
| Patent application number | Description | Published |
|---|---|---|
| 20100170101 | CLOTH DRYER - A cloth dryer includes heat-pump ( | 07-08-2010 |
Masayuki Tanaka, Kawasaki JP
| Patent application number | Description | Published |
|---|---|---|
| 20100119007 | PRECODER CIRCUIT - A disclosed precoder circuit is used for differential phase shift keying and includes multiple levels of parallel precoder units, each of which is configured to perform a precoding operation using a data signal having multiple symbols and one of a fixed value and a one-symbol preceding modulated signal output from a preceding-level parallel precoder unit so as to obtain a modulated signal, precoding operations of the parallel precoder units being simultaneously performed in a parallel fashion; multiple levels of re-timing units configured to synchronize modulated signals output from the parallel precoder units; and multiple levels of offset units, each of which is configured to add a phase difference between the fixed value and the one-symbol preceding modulated signal to the modulated signals output from the corresponding re-timing units. | 05-13-2010 |
| 20110154159 | CYCLIC REDUNDANCY CHECK CODE GENERATING CIRCUIT AND CYCLIC REDUNDANCY CHECK CODE GENERATING METHOD - A cyclic redundancy check code generating circuit successively receives one or more parallel data as input, and repetitively performs a prescribed operation for calculating a cyclic redundancy check code for each parallel data, based on the parallel data and on an initial value or an earlier calculated cyclic redundancy check code. The cyclic redundancy check code generating circuit includes: a plurality of sub-operation units which, based on the initial value and the parallel data, perform sub-operations in different pipeline stages, respectively, by dividing the prescribed operation in a bit length direction of the parallel data; and a correction unit which, based on the initial value and the earlier calculated cyclic redundancy check code, corrects the cyclic redundancy check code calculated by the sub-operation units. | 06-23-2011 |
Masayuki Tanaka, Kawasaki-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100049489 | FLOW SIMULATION METHOD, FLOW SIMULATION SYSTEM, AND COMPUTER PROGRAM PRODUCT - A system for a flow simulation using Moving Particle Semi-implicit method, includes a processor representing a target incompressible fluid by a plurality of particles grouped according to different particle sizes depending on a spatial resolution required at positions in a simulation domain; temporarily updating a velocity and a position coordinate of each particle to a first velocity and a first position coordinate by implicitly calculating a variation of the velocity of each particle due to a viscosity of the incompressible fluid in each of a plurality of time steps having a predetermined time interval; and updating the first velocity and the first position coordinate to a second velocity and a second position coordinate of each particle at a next time step of each time step by calculating a velocity correction of the first velocity due to a pressure gradient of the incompressible fluid using the first velocity. | 02-25-2010 |
| 20110195115 | HYDROPHILIC AMINO ACID-CONTAINING PREPARATION HAVING IMPROVED TASTE - The present invention provides a hydrophilic amino acid-containing preparation wherein the taste of the hydrophilic amino acid is improved without damaging the appearance, flavor, storage stability and so on. It is further intended to provide a hydrophilic amino acid-containing preparation in which quick release of the hydrophilic amino acid from the preparation is assured, if necessary. It is furthermore intended to provide a hydrophilic amino acid-containing preparation where a solid agent containing a hydrophilic amino acid is coated with a coating agent comprising a flavoring agent and a water-soluble high molecular material. | 08-11-2011 |
Masayuki Tanaka, Nirasaki-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090151639 | Gas processing apparatus and gas processing method - A gas processing apparatus | 06-18-2009 |
| 20090211526 | PROCESSING APPARATUS USING SOURCE GAS AND REACTIVE GAS - The present invention relates to a processing apparatus for performing a film-deposition process or the like for an object to be processed (such as a semiconductor wafer) by means of a source gas and a reactive gas. The processing apparatus includes: a processing vessel ( | 08-27-2009 |
Masayuki Tanaka, Sagamihara-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090082968 | MATERIAL HANDLING VEHICLE LOCATION SYSTEM - The object of the invention is to provide a system which can be constituted quite compactly for detecting actual position of a material handling vehicle in a warehouse in which a plurality of racks composed of upright frame members and lateral frame members connecting the upright members are installed so that material handling vehicles can travel along the passageway between the racks so that current position of the material handling vehicle in the warehouse can be detected with increased reliability even if some of the reflections fail to be received by the sensors. | 03-26-2009 |
Masayuki Tanaka, Kyoto JP
| Patent application number | Description | Published |
|---|---|---|
| 20110120849 | OPERATION INPUT DEVICE AND ELECTRONIC DEVICE USING THE SAME - An operation input device includes a base including at least four elastic engagement receiving portions raised at a periphery of a center thereof; a print substrate configured to be stacked and integrated on the base; an annular operation plate mounted on push button switches of the print substrate and configured to prevent slip-out; an operation dial mounted on the annular operation plate on an axial center; and a fixing tool configured to be inserted to a fit-in hole of the operation hole and engage with at least two elastic engagement receiving portions of the base at an edge on a lower side and with an inner peripheral edge of the operation dial. | 05-26-2011 |
Masayuki Tanaka, Yamatotakada-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110203869 | ELECTRIC POWER STEERING APPARATUS - In an electric power steering apparatus including capacitor for smoothing out the voltage of battery and relay including a relay contact disposed at a place upstream of the capacitor, a path is provided for directly conducting a terminal voltage of the capacitor from a downstream side of the relay contact to a system power supply supply that generates a source voltage for a control system including controller and the like, so that the system power supply and the control system that is supplied therefrom with electric power for control purpose are utilized as a discharge circuit. Thus is obtained a simplified configuration of circuit responsible for discharging the capacitor. | 08-25-2011 |
Masayuki Tanaka, Kanagawa-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20110316066 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a tunnel insulating film, a first electrode, an interelectrode insulating film and a second electrode. The tunnel insulating film is provided on the semiconductor substrate. The first electrode is provided on the tunnel insulating film. The interelectrode insulating film is provided on the first electrode. The second electrode is provided on the interelectrode insulating film. The interelectrode insulating film includes a stacked insulating layer, a charge storage layer and a block insulating layer. The charge storage layer is provided on the stacked insulating layer. The block insulating layer is provided on the charge storage layer. The stacked insulating layer includes a first insulating layer, a quantum effect layer and a second insulating layer. The quantum effect layer is provided on the first insulating layer. The second insulating layer is provided on the quantum effect layer. | 12-29-2011 |