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Masayuki Nakamura
Masayuki Nakamura, Saitama JP
| Patent application number | Description | Published |
|---|---|---|
| 20110102038 | DUTY RATIO CONTROL APPARATUS AND DUTY RATIO CONTROL METHOD - There are provided a duty ratio control apparatus for altering a duty ratio of a clock signal to output an altered clock signal, including a first variable delay section that outputs a first delayed clock signal generated by delaying the clock signal by a predetermined first delay time, and a phase comparing section that compares, in terms of phase, an edge of the clock signal and an edge of the first delayed clock signal and generates the altered clock signal having a pulse width determined by a phase difference obtained by the comparison, and a duty ratio control method. | 05-05-2011 |
| 20120040234 | LAMINATED BATTERY AND MANUFACTURING METHOD THEREOF - A laminated battery formed by laminating a plurality of flat cells each having an electrode tab includes: an insulating member disposed to prevent a short-circuit in the electrode tab; and a terminal connected to the electrode tab, wherein a tip end side of the terminal is supported by a support member provided on the insulating member. | 02-16-2012 |
Masayuki Nakamura, Iwate JP
| Patent application number | Description | Published |
|---|---|---|
| 20100279108 | RESIN- METAL BONDED BODY AND METHOD FOR PRODUCING THE SAME - Disclosed is a resin-metal bonded body of an aluminum metal member and a thermoplastic resin member, which has improved bonding strength and good durability. Also disclosed is a method for producing such a resin-metal bonded body. Specifically disclosed is a resin-metal bonded body which is obtained by bonding an aluminum metal member with a thermoplastic resin member. In this resin-metal bonded body, the aluminum metal member and the thermoplastic resin member are bonded together by an anodic oxide coating having a film thickness of 70-1500 nm or an anodic oxide coating having a triazine thiol in the inner and upper portions. The anodic oxide coating has an infrared absorption spectrum peak intensity ascribed to OH group at 0.0001-0.16. | 11-04-2010 |
| 20110033711 | RESIN-METAL BONDED ARTICLE AND METHOD FOR PRODUCING THE SAME - Disclosed is a resin-metal bonded article which is improved in adhesion between a copper component and a PPS or PBT resin. Also disclosed is a method for producing such a resin-metal bonded article. The resin-metal bonded article is obtained by bonding the resin component onto the surface of the copper component through a copper component bonding surface where there is copper oxide in the following range: 10%≦Cu | 02-10-2011 |
Masayuki Nakamura, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20080239865 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature. | 10-02-2008 |
| 20080273413 | SEMICONDUCTOR DEVICE - A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode. | 11-06-2008 |
| 20090002048 | Reference voltage generating circuit - Disclosed is a reference voltage generating circuit which includes resistors R | 01-01-2009 |
| 20090302908 | OSCILLATOR AND A TUNING METHOD OF A LOOP BANDWIDTH OF A PHASE-LOCKED-LOOP - There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal. | 12-10-2009 |
| 20100309706 | Load reduced memory module and memory system including the same - A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate. | 12-09-2010 |
| 20100312925 | Load reduced memory module - A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate. | 12-09-2010 |
| 20100312956 | Load reduced memory module - A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate. | 12-09-2010 |
Masayuki Nakamura, Yokohama JP
| Patent application number | Description | Published |
|---|---|---|
| 20090322759 | LINE PLOTTING METHOD - A line plotting method for plotting lines whose coordinates are given on a display screen on which pixels are arranged according to a prescribed rule, the method includes correcting coordinates at the end point of a line on the basis of which the end point is a starting point or an ending point or whether the end point is inside a prescribed frame determining whether a direction from a starting point of a line after correction toward its ending point horizontally or vertically is the same as a direction from a starting point before correction of a line toward its ending point determining whether integer values of the coordinates of starting and ending points after correction are the same when directions from starting points after and before correction of a line toward their ending points are not matched. | 12-31-2009 |
| 20100123728 | MEMORY ACCESS CONTROL CIRCUIT AND IMAGE PROCESSING SYSTEM - A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit. | 05-20-2010 |
Masayuki Nakamura, Sagamihara JP
| Patent application number | Description | Published |
|---|---|---|
| 20090278459 | INDUCTION COIL, A PLASMA GENERATOR AND A PLASMA GENERATING METHOD - The plasma generator of our invention comprises of the induction coil which is symmetric with respect to the reference plane between two terminal ends. Plasma processing gas is supplied to a predetermined space, and high frequency electricity is supplied to the induction coil, thereby the plasma generator generates plasma in the space. The reference plane passes between the two terminal ends and through longitude axis of the induction coil. The plasma generator can generate plasma with high quality of homogeneous. | 11-12-2009 |
Masayuki Nakamura, Ibaraki JP
| Patent application number | Description | Published |
|---|---|---|
| 20090270436 | SPIROCHROMANON DERIVATIVES - The invention relates to a compound of a general formula (I): wherein Ar1 represents a group formed from an aromatic ring selected from a group consisting of benzene, pyrazole, isoxazole, pyridine, indole, 1H-indazole, 1H-furo[2,3-c]pyrazole, 1H-thieno[2,3-c]pyrazole, benzimidazole, 1,2-benzisoxazole, imidazo[1,2-a]pyridine, imidazo[1,5-a]pyridine and 1H-pyrazolo[3,4-b]pyridine, having Ar2, and optionally having one or two or more substituents selected from R3: R1 and R2 each independently represent a hydrogen atom, a halogen atom, a cyano group, a C2-C6 alkenyl group, a C1-C6 alkoxy group, a C2-C7 alkanoyl group, a C2-C7 alkoxycarbonyl group, an aralkyloxycarbonyl group, a carbamoyl-C1-C6 alkoxy group, a carboxy-C2-C6 alkenyl group, or a group of -Q1-N(Ra)-Q2-Rb; or a C1-C6 alkyl group optionally having a substituent; or an aryl or heterocyclic group optionally having a substituent; or a C1-C6 alkyl group or a C2-C6 alkenyl group having the aryl or heterocyclic group; T and U each independently represent a nitrogen atom or a machine group; and V represents an oxygen atom or a sulfur atom. The compound of the invention is useful as therapeutical agents for various ACC-related diseases. | 10-29-2009 |
Masayuki Nakamura, Nagano JP
| Patent application number | Description | Published |
|---|---|---|
| 20080318897 | Composition Containing Swelling Agent Composed of Swellable Water-Soluble Polysaccharide, and Food, Anti-Obesity Agent and Constipation Alleviator Each Containing the Composition - A composition containing a swelling agent is provided, which less burdens the stomach and intestine even after excessive intake. A food, anti-obesity agent and constipation alleviator each containing the composition is also provided. | 12-25-2008 |
Masayuki Nakamura, Woodbury, MN US
| Patent application number | Description | Published |
|---|---|---|
| 20080264849 | SINGLE PASS METHOD AND APPARATUS FOR SEPARATING A TARGET MOLECULE FROM A LIQUID MIXTURE - A single pass simulated moving bed apparatus and methods are described for continuously separating a target molecule from a liquid mixture, using a simulated moving bed system. The simulated moving bed system includes a plurality of filter cartridge modules in serial fluid communication. Each filter cartridge module includes a volume of stationary phase particulates adjacent a porous substrate layer. The volume of stationary phase particulates has a bed height of less than 1 centimeter. | 10-30-2008 |
Masayuki Nakamura, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20120074018 | EMBOSSING DEVICE, EMBOSSING METHOD, AND EMBOSSED CAN - To provide an embossing device, an embossing method and an embossed can which are capable of conducting embossing having a non-shaped section and an arbitral number of embossed areas, and are capable of improving quality or productivity. | 03-29-2012 |