| Patent application number | Description | Published |
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| 20080218225 | Semiconductor Device and Communication Control Method - The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B. The controller controls in such way that the core B can receive only the data arriving prior to the setup of the clock signal clkB. The controller stores the history on a communication status between cores. | 09-11-2008 |
| 20090001348 | SEMICONDUCTOR DEVICE - A programmable semiconductor device has a switch element in an interconnection layer, wherein in at least one of the inside of a via, interconnecting a wire of a first interconnection layer and a wire of a second interconnection layer, a contact part of the via with the wire of the first interconnection layer and a contact part of the via with the wire of the second interconnection layer, there is provided a variable electrical conductivity member, such as a member of an electrolyte material. The via is used as a variable electrical conductivity type switch element or as a variable resistance device having a contact part with the wire of the first interconnection layer as a first terminal and having a contact part with the wire of the second interconnection layer as a second terminal. | 01-01-2009 |
| 20090029308 | HEAT SHIELD PLATE FOR SUBSTRATE ANNEALING APPARATUS - A heat shield plate for a substrate annealing apparatus is provided with a horizontally supported flat-plate-like substrate | 01-29-2009 |
| 20090128134 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS, MEASUREMENT RESULT MANAGEMENT SYSTEM, AND MANAGEMENT SERVER - A semiconductor integrated circuit apparatus, and more particularly a technology for measuring and managing a physical amount of factors that exert an influence upon an operation of a semiconductor integrated circuit is provided; more particularly, a semiconductor integrated circuit that is an object of measurement, and a measurement circuit which measures a physical factor that exerts an influence upon the actual operation of the semiconductor integrated circuit, such as jitter or noise jitter, and noise of this semiconductor integrated circuit are provided on an identical chip; also, a measurement result of the measurement circuit of the present invention is analyzed, and is fed back to a circuit for adjusting the semiconductor integrated circuit that is the object of measurement. | 05-21-2009 |
| 20090134524 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor device comprising a signal transmission line of a microstrip structure, capable of increasing the characteristic impedance of the signal transmission line and reducing coupling between a plurality of signal lines. In a signal transmission line of a microstrip structure composed of a signal line and a ground plate, the capacitance between wires is reduced and the characteristic impedance can be increased by forming holes in the signal line or in the ground plate. The coupling between a plurality of signal lines can also be reduced. | 05-28-2009 |
| 20090146640 | PHASE DIFFERENCE MEASURING DEVICE AND PHASE COMPARISON CIRCUIT ADJUSTING METHOD - A phase difference measuring device according to this invention has an object of shortening the measuring time, and includes a plurality of phase difference measuring circuits ( | 06-11-2009 |
| 20090189596 | SIGNAL MEASURING DEVICE - An interpolated signal generating circuit ( | 07-30-2009 |
| 20090201045 | INPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT COMPRISING THE INPUT CIRCUIT - A control signal input circuit for supplying control signals to a plurality of controlled circuits comprises N pieces of control signal preservation/output circuits provided one by one corresponding to plural-bit signals for delivering input data as it is when a trigger signal is at a first level, and holding previously delivered output data when the trigger signal is at a second level, and a controlled circuit selector circuit for setting the trigger signal for S pieces of the control signal preservation/output circuits to the first level, and setting the trigger signal for the rest of the control signal preservation/output circuits to the second level. | 08-13-2009 |
| 20090240980 | INFORMATION PROCESSING DEVICE AND FAILURE CONCEALING METHOD THEREFOR - An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit. | 09-24-2009 |
| 20090243624 | SIGNAL MEASURING DEVICE - Small-scale measuring circuits ( | 10-01-2009 |
| 20090269084 | LIGHT RECEIVING CIRCUIT AND DIGITAL SYSTEM - A light receiving circuit ( | 10-29-2009 |
| 20090271594 | SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT CONTROL DEVICE, LOAD DISTRIBUTION METHOD, LOAD DISTRIBUTION PROGRAM, AND ELECTRONIC DEVICE - A damage control unit includes: a switching judgment unit to judge the CPU configuration which performs smoothing of the damage ratio, according to the damage ratio of the CPUs; and a switching unit to perform switching of I/O signals of all the CPUs. The switching judgment unit observes the damage ratio calculated from values such as the temperature, voltage, current consumption amount, operation ratio, the number of accesses to the resources in the CPU, at all times or at some extent of time intervals and notifies the switching unit of the CPU configuration to be changed by using the calculation method for smoothing the damage ratio of each CPU. The switching unit makes a connection to the I/O signals of all the CPUs and a system bus and switches the I/O signal of the CPU to be switched according to the notification from the switching judgment unit. | 10-29-2009 |
| 20100033239 | SEMICONDUCTOR DEVICE - A main chip has a signal processing circuit for executing signal processing; a plurality of signal transmitting circuits for transmitting signals between the signal processing circuit and a signal transmitting circuit; and a control circuit for controlling operation/non-operation of the signal transmitting circuits in accordance with signal processing content of the signal processing circuit. Functional chips each have a signal processing circuit for executing auxiliary signal processing different from that of the signal processing circuit; and one or a plurality of signal transmitting circuits for transmitting signals between the signal processing circuit and the signal transmitting circuits. The main chip and the functional chips are stacked. The signal transmitting circuits and the signal transmitting circuit are non-contact-type signal transmitting circuits utilizing inductive coupling and are arranged so as to overlap when viewed from the stacking direction. | 02-11-2010 |
| 20100042373 | SIGNAL MEASURING DEVICE AND SIGNAL MEASURING METHOD - A signal measuring device, comprises one set, or a plurality of sets, of measuring unit(s) measuring an object of measurement in synch with a driving clock signal for measurement and outputting result of measurement as first data, and a timing identification unit which, in accordance with a measurement-start command, outputs a value, which differs every period, as second data in synch with a reference signal having a prescribed period and a speed lower than that of the driving clock signal; and a storage unit collecting and successively storing the first data and the second data as one set in synch with the driving clock signal. | 02-18-2010 |
| 20100045332 | TEST CIRCUIT, METHOD, AND SEMICONDUCTOR DEVICE - It is possible to provide a circuit and method for carrying out a parallel test using BOST (Built Out Self Test). The circuit includes first transfer circuits ( | 02-25-2010 |
| 20100045372 | AMPLIFICATION CIRCUIT, AMPLIFICATION CIRCUIT NOISE REDUCING METHOD AND PROGRAM THEREOF - [Problems] to provide a CMOS low-noise amplification circuit which can reduce a chip area and design time, and which is easy to be digital-controlled from outside. | 02-25-2010 |
| 20100052724 | CIRCUIT AND METHOD FOR PARALLEL TESTING AND SEMICONDUCTOR DEVICE - Disclosed is a test circuit including a first transfer circuit, a second transfer circuit and comparators and performing parallel testing of a plurality of chips under test. The first transfer circuit includes flip-flops. A data pattern from a tester is supplied to the initial stage chip under test. To the remaining chips under test, output data from the corresponding stages of the first transfer circuit are supplied. The second transfer circuit sequentially transfers an output of the initial stage chip under test, as an expected value pattern, in response to clock cycles. The comparator compares output data of the chip under test with an expected value pattern from the corresponding stage of the second transfer circuit. | 03-04-2010 |
| 20100052753 | CLOCK SIGNAL DIVIDING CIRCUIT - A clock signal dividing circuit in which a dividing ratio is regulated by N/M (M and N are positive integers and satisfy M>N) includes: a variable delay circuit which gives a predetermined delay amount based on a control value to an input clock signal CKI to output an output clock signal CKO; and a variable delay control circuit which cumulatively adds values obtained by subtracting N from M every cycle of the input clock signal CKI, when the addition result is N or more, performs a calculation which subtracts N from the addition result to obtain a calculation result K, and calculates, to a maximum delay amount in the variable delay circuit corresponding to one cycle of the input clock signal CKI, a control value corresponding to a delay amount of K/N of the maximum delay amount to give the control value to the variable delay circuit. | 03-04-2010 |
| 20100052792 | AMPLIFYING APPARATUS, METHOD OF OUTPUT CONTROL AND CONTROL PROGRAM - [PROBLEMS] To provide, for example, a pulse input type power amplifying apparatus that can be operated at low voltage and low power, effectively suppressing generation of harmonic component. | 03-04-2010 |
| 20100066401 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device in which a circuit in the semiconductor chip is divided into a plurality of sub-circuits. The semiconductor device includes switches between the respective sub-circuits and a power supply, and a circuit that variably controls on-resistances of the switches | 03-18-2010 |
| 20100077259 | APPARATUS AND METHOD FOR PERFORMING A SCREENING TEST OF SEMICONDUCTOR INTEGRATED CIRCUITS - An apparatus for performing a screening test of a semiconductor integrated circuit is disclosed, the semiconductor integrated circuit comprising a plurality of processors each having an output signal for instruction execution information, and the processors being programmatically operable. The apparatus for performing a screening test of a semiconductor integrated circuit comprises: an instruction/data signal synchronization circuit for synchronizing the supplying of instructions to said respective processors and for synchronizing the supplying of data to said respective processors; and a trace comparison circuit for comparing instruction execution information that are output from the respective processors to determine whether or not any of said processors has output different instruction execution information. | 03-25-2010 |
| 20100094577 | SIGNAL QUALITY MEASUREMENT DEVICE, SPECTRUM MEASUREMENT CIRCUIT, AND PROGRAM - Spectrum measurement circuit ( | 04-15-2010 |
| 20100100886 | TASK GROUP ALLOCATING METHOD, TASK GROUP ALLOCATING DEVICE, TASK GROUP ALLOCATING PROGRAM, PROCESSOR AND COMPUTER - Even if a multiprocessor includes an uneven performance core, an inoperative core or a core that does not satisfy such a performance as designed but if the contrivance of task allocation can satisfy the requirement of an application to be executed, the multiple processors are shipped. In a task group allocation method for allocating, to a processor having a plurality of cores, task groups included in an application for the processor to execute, a calculation section measures performances and disposition patterns of the cores, generates a restricting condition associating the measured performances and disposition patterns of the cores with information indicating whether the application can be executed, and, with reference to the restricting condition, reallocates to the cores, the task groups that have previously been allocated to the cores. | 04-22-2010 |
| 20100153784 | SEMICONDUCTOR INTEGRATED CIRCUITS AND METHOD OF DETECTING FAULTS OF PROCESSORS - A semiconductor integrated circuit comprising a processor having an output signal of instruction log information and being operable in a program in memory is disclosed. The semiconductor integrated circuit comprises trace determination circuit for comparing an instruction code that corresponds to the instruction log information from a processor with an instruction code that is read from the memory to detect faults. | 06-17-2010 |
| 20100164053 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling. | 07-01-2010 |
| 20100176893 | MODULATION DEVICE AND PULSE WAVE GENERATION DEVICE - Provided is a modulation device including a signal selection circuit selecting two carrier signals from a plurality of carrier signals having the same frequency and the same phase difference according to a defined control signal and outputting the selected carrier signals, and a phase interpolator adjusting the phase in smaller units than the phase difference between the plurality of carrier signals according to the control signal and modulating the frequency or the phase of the carrier signal into a baseband signal based on the carrier signals selected by the signal selection circuit to generate a carrier wave signal. | 07-15-2010 |
| 20100251046 | FAILURE PREDICTION CIRCUIT AND METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT - Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs. | 09-30-2010 |
| 20100259292 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND TEST METHOD THEREFOR - A semiconductor integrated circuit device includes: a normal output signal counter that counts number of times a normal output signal is output by the circuit under test in response to a preset one of the input signals of the input signal set, in case where a circuit under test repeats processing on each of one or more input signals of an input signal set sequentially, a plural number of times. | 10-14-2010 |
| 20100272149 | TEMPERATURE MEASURING DEVICE AND METHOD - Current reading means detects an output current of a current source whose output current varies with a variation in temperature and outputs a value proportional to the output current. The temperature of the current source corresponding to the output value of the current reading means which is proportional to the output current of the current source is measured, and a parameter for converting the output value to temperature information is determined from the output value of the current reading means and the measured value of the temperature of the current source corresponding to the output value. The output value of the current reading means is converted to the temperature information using the determined parameter. | 10-28-2010 |
| 20100283497 | SEMICONDUCTOR TESTING DEVICE, SEMICONDUCTOR DEVICE, AND TESTING METHOD - A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses ( | 11-11-2010 |
| 20110007554 | SEMICONDUCTOR DEVICE - A programmable semiconductor device has a switch element in an interconnection layer, wherein in at least one of the inside of a via, interconnecting a wire of a first interconnection layer and a wire of a second interconnection layer, a contact part of the via with the wire of the first interconnection layer and a contact part of the via with the wire of the second interconnection layer, there is provided a variable electrical conductivity member, such as a member of an electrolyte material. The via is used as a variable electrical conductivity type switch element or as a variable resistance device having a contact part with the wire of the first interconnection layer as a first terminal and having a contact part with the wire of the second interconnection layer as a second terminal. | 01-13-2011 |
