Patent application number | Description | Published |
20090026537 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device formed with a trench portion for providing a concave portion in a gate width direction and with a gate electrode provided within and on a top surface of the trench portion via a gate insulating film. At least a part of a surface of each of the source region and the drain region is made lower than other parts of the surface by removing a thick oxide film formed in the vicinity of the gate electrode. Making lower the part of the surface of each of the source region and the drain region allows current flowing through a top surface of the concave portion of the gate electrode at high concentration to flow uniformly through the entire trench portion, which increase an effective gate width of the concave portion formed so as to have a varying depth in a gate width direction. | 01-29-2009 |
20090026538 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device formed with a trench portion for providing a concave portion having a continually varying depth in a gate width direction and with a gate electrode provided within the trench portion and on a top surface thereof via a gate insulating film. Before the formation of the gate electrode, an impurity is added to at least a part of the source region and the drain region by ion implantation from an inner wall of the trench portion, and then heat treatment is performed for diffusion and activation to form a diffusion region from the surface of the trench portion down to a bottom portion thereof. Current flowing through a top surface of the concave portion of the gate electrode at high concentration can flow uniformly through the entire trench portion. | 01-29-2009 |
20120007174 | Semiconductor device and method of manufacturing the same - The semiconductor device includes a trench having a depth of a distance equal to or shorter than the L length of the transistor, and a buried layer is used in a bottom portion of the trench, whereby an effective channel length from each of a lower end of a high concentration source diffusion layer and a lower end of a high concentration drain diffusion layer to a bottom surface of the trench is made shorter than the shortest length L on a top surface of the trench. Accordingly, a current path is held on the bottom surface of the trench from a side surface thereof which contacts with the source or high concentration drain diffusion layer with a use of the buried layer, whereby the driving performance is enhanced. An effect of suppressing the decrease of the driving performance is obtained for the reduced gate length. | 01-12-2012 |
Patent application number | Description | Published |
20130168763 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An oxide film is formed by STI in a silicon surface region in which a substrate potential heavily doped diffusion layer and a source heavily doped diffusion layer are to be provided later between trenches at predetermined intervals. The oxide film is removed after the trench is formed, to thereby form a region which is lower than a surrounding surface. Thus, in the vertical MOS transistor having a trench structure which includes a side spacer, a silicide on a gate electrode embedded in the trench and a silicide on the substrate potential heavily doped diffusion layer and the source heavily doped diffusion layer can be separated from each other. | 07-04-2013 |
20130207636 | REFERENCE VOLTAGE GENERATOR - Provided is a reference voltage generator having flat temperature characteristics. The reference voltage generator includes: a depletion mode MOS transistor ( | 08-15-2013 |
20140084378 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged. | 03-27-2014 |
20140191313 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device formed with a trench portion for providing a concave portion in a gate width direction and with a gate electrode provided within and on a top surface of the trench portion via a gate insulating film. At least a part of a surface of each of the source region and the drain region is made lower than other parts of the surface by removing a thick oxide film formed in the vicinity of the gate electrode. Making lower the part of the surface of each of the source region and the drain region allows current flowing through a top surface of the concave portion of the gate electrode at high concentration to flow uniformly through the entire trench portion, which increase an effective gate width of the concave portion formed so as to have a varying depth in a gate width direction. | 07-10-2014 |