Patent application number | Description | Published |
20090295478 | AMPLIFIER USING IMPEDANCE CIRCUIT FOR CANCELING CUTOFF - An amplifier circuit includes a pair of transistors amplifying differential signals of input signals to respective input terminals and outputting differential output signals to respective output terminals, and an impedance circuit provided in between sources of the pair of transistors, canceling a first cutoff characteristic on a high frequency side in frequency characteristics of the amplifier circuit constructed of the pair of transistors, and forming a second cutoff characteristic on a higher frequency side than the first cutoff characteristic. | 12-03-2009 |
20100026536 | SAMPLE-HOLD CIRCUIT HAVING SPREADING SWITCH AND ANALOG-DIGITAL CONVERTER USING SAME - A sample-hold circuit includes a voltage-current converter, having a first input terminal pair to which an input differential signal is input and a first output terminal pair which outputs current according to the voltage of the input differential signal, a spreading switch having a switch group which switches the first output terminal pair to inverting or non-inverting states, and an integrator having a second input terminal pair coupled to the first output terminal pair via the spreading switch, an output amplifier which outputs to a second output terminal pair an output differential signal amplified according to the differential signal at the second input terminal pair, a capacitor pair which is provided respectively between the second input terminal pair and second output terminal pair, and which is charged or discharged by current input to the second input terminal pair, and a reset circuit which resets charge states of the capacitor pair. | 02-04-2010 |
20100039305 | COMPARATOR CIRCUIT AND ANALOG DIGITAL CONVERTER HAVING THE SAME - A comparator circuit includes a first comparator comparing an input signal to a first comparison value and generating a first determination signal, a second comparator comparing the input signal to a second comparison value different from the first comparison value and generating a second determination signal, and an output selecting circuit selecting a signal generated first from the first determination signal and the second determination signal, and outputting the selected signal as a determination signal. | 02-18-2010 |
20100265113 | CHARGE REDISTRIBUTION DIGITAL-TO-ANALOG CONVERTER, AND SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER HAVING THE SAME - A D/A converter includes plus-side and minus-side input terminals; plus-side and minus-side D/A converters each including plural plus-side or minus-side capacitors having capacitance values weighted by the powers of two, a plus-side or minus-side output terminals connected to first electrodes of the plus-side or minus-side capacitors, and plural plus-side or minus-side switches for connecting each second electrode of the plus-side or minus-side capacitors to either the plus-side or minus-side input terminal, a plus-side reference voltage terminal or a minus-side reference voltage terminal according to plus-side or minus-side control digital signals; and plural short-circuit switches provided between identically weighted plus-side and minus-side capacitors respectively. And, at the time of sampling, the plus-side and minus-side switches connect the second electrodes of the capacitors to the plus-side and minus-side input terminals, respectively, and, after the sampling, the plurality of short-circuit switches short-circuit between the second electrodes of the plus-side and minus-side capacitors. | 10-21-2010 |
20110063147 | SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER (ADC) AND METHOD OF ADJUSTING DELAY THEREOF - A successive approximation register analog-to-digital converter includes: a digital-to-analog converter that generates an analog voltage based on a digital code; a comparator that receives the analog voltage; a control circuit that generates a digital code of an input voltage sampled from an external clock signal by successively changing the digital code based on a comparison result of the comparator; a delay circuit that resets the comparator based on a signal transition generated by delaying the comparison result; and an adjustment circuit that counts a value indicating a number of the signal transition being generated during a cycle of the external clock signal and adjusts a delay of the delay circuit according to a counted value. | 03-17-2011 |
20120032824 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER, AND OPERATING CLOCK ADJUSTMENT METHOD THEREFOR - A successive approximation register analog-to-digital converter includes: a digital-to-analog converter to generate an analog voltage based on an input voltage sampled in accordance with a sampling clock and a digital code; a comparator to receive the analog voltage; a controller to generate the digital code based on an output of the comparator; a delay circuit to delay a signal based on the output of the comparator and to feed back the delayed signal to a reset terminal of the comparator; an adjustment circuit to count a number of edges of a signal generated in a loop that feeds back the delayed signal, and to adjust an amount of delay of the delay circuit based on a count value; and a sampling clock generation circuit to generate the sampling clock based on the signal generated in the loop and the external clock signal. | 02-09-2012 |
20130321189 | AD CONVERTER CIRCUIT AND AD CONVERSION METHOD - A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit. | 12-05-2013 |
20140293738 | GAIN CONTROL CIRCUIT AND ULTRASONIC IMAGE DEVICE - A gain control circuit includes: a voltage generation circuit that generates first voltage that is linearly changed over time; a voltage square circuit that outputs second voltage that is obtained by squaring the first voltage generated by the voltage generation circuit; a resistance circuit that has a resistance characteristic by which a resistance value is squared-changed over time depending on the second voltage output from the voltage square circuit; and a gain adjustment circuit in which gain is squared-changed over time depending on the resistance value of the resistance circuit. | 10-02-2014 |