Patent application number | Description | Published |
20080256550 | Parallel processing system by OS for single processor - The present invention relates to a parallel processing system by an OS for single processor capable of operating an OS for single processor and an existing application on a multiprocessor and achieving parallel processing by a multiprocessor with respect to the application, wherein the multiprocessor are logically divided into two groups, i.e., a first processor side and a second processor side, and units of work that are parallelizable within the application operating on the processors on the first processor side are controlled as new units of work on the processors on the second processor side. | 10-16-2008 |
20090119541 | Information Processing Device, Recovery Device, Program and Recovery Method - The information processing device which recovers a domain developing a fault caused by added application and device driver while maintaining security and reliability includes a plurality of processors, wherein the plurality of processors form a plurality of domains according to processing contents to be executed, and the processors in different domains communicate with each other through a communication unit, and which further includes a recovery unit for executing, for a domain developing a fault, failure recovery processing based on a failure recovery request notified by the domain and a recovery condition set in advance for each domain. | 05-07-2009 |
20090247142 | INFORMATION COMMUNICATION PROCESSING DEVICE, INFORMATION COMMUNICATION TERMINAL, INFORMATION COMMUNICATION SYSTEM, FUNCTION SWITCHING METHOD AND FUNCTION SWITCHING PROGRAM - Provided is the information communication processing device capable of executing terminal function switching control in linkage with an external communication content on one information communication processing device based on the external communication content without a problem in switching. The information communication processing device has at least one information processing device having a plurality of function environments for executing an application, and a switching control unit for switching a function environment, in which the switching control unit determines a function environment to be switched based on contents of communication with the outside of the information communication processing device and sets context of the function environment to be switched at context of a function environment being executed, thereby executing switching to the function environment to be switched. | 10-01-2009 |
20100031008 | PARALLEL SORTING APPARATUS, METHOD, AND PROGRAM - A parallel sorting apparatus is provided whose sorting processing is speeded up. A reference value calculation section calculates a plurality of reference values serving as boundaries of intervals used for allocating input data depending on the magnitude of a value. An input data aggregation section partitions the input data into a plurality of input data regions, and calculates, by parallel processing, mapping information used for allocating data in each of the partitioned input data regions to the plurality of intervals that have boundaries on the reference values calculated by the reference value calculation section. A data allocation section allocates, by parallel processing, data in each of the input data regions to the plurality of intervals in accordance with the mapping information calculated by the input data aggregation section. An interval sorting section individually sorts, by parallel processing, data in the plurality of intervals allocated by the data allocation section. | 02-04-2010 |
20100100706 | MULTIPLE PROCESSOR SYSTEM, SYSTEM STRUCTURING METHOD IN MULTIPLE PROCESSOR SYSTEM AND PROGRAM THEREOF - For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit | 04-22-2010 |
20100172366 | SEMICONDUCTOR INTEGRATED CIRCUIT AND FILTER CONTROL METHOD - A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information. | 07-08-2010 |
20100183015 | SEMICONDUCTOR INTEGRATED CIRCUIT AND FILTER CONTROL METHOD - A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set. | 07-22-2010 |
20100199052 | INFORMATION PROCESSING APPARATUS, EXECUTION ENVIRONMENT TRANSFERRING METHOD AND PROGRAM THEREOF - Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory. | 08-05-2010 |
20120331474 | REAL TIME SYSTEM TASK CONFIGURATION OPTIMIZATION SYSTEM FOR MULTI-CORE PROCESSORS, AND METHOD AND PROGRAM - Disclosed is an automatic optimization system capable of searching for an allocation with a good performance from among a plurality of task allocations which can be scheduled in a system of a development target configured with a plurality of periodic tasks. A task allocation optimization system for a multi-core processor including a plurality of cores calculates a response time of each of a plurality of tasks which are core allocation decision targets, and outputs an accumulative value of the calculated response time as an evaluation function value which is an index representing excellence of a task allocation. A task allocation from which a good evaluation function value is calculated is searched based on the evaluation function value. A candidate having a good evaluation function value among a plurality of searched task allocation candidates is held. | 12-27-2012 |