Patent application number | Description | Published |
20090006876 | STORAGE SYSTEM COMPRISING FUNCTION FOR REDUCING POWER CONSUMPTION - For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state. | 01-01-2009 |
20090006890 | Storage system and control method of storage system - Provided is a storage system superior in fault tolerance. This storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates such failed component. Further, after invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting itself. | 01-01-2009 |
20090316541 | STORAGE APPARATUS AND ESTIMATING METHOD OF POWER CONSUMPTION FOR STORAGE APPARATUS - Power consumption is calculated in accordance with an operation state of disk devices without using a power meter in a storage system. The power consumption in accordance with the operation state is calculated as follows. That is, information on the power consumption for every type of hard disks is stored in advance when types of I/O process (random/sequential of read and write) operate at idle time up to a limit state in every type of hard disks. A control unit of the storage system aggregates time waiting a response from the hard disks in every type of I/O process. The power consumption of the disks is calculated on the basis of the information on the power consumption stored in advance and a sum of the waiting time of the response from the hard disks. | 12-24-2009 |
20100011238 | INFORMATION PROCESSING SYSTEM AND DATA RECOVERY METHOD - When data of HDD of computer is backed up to a a data center and a failure occurs in the HDD, the computer notifies failure information to the data center, and the data center stores the backed up data in a storage medium substituting HDD for subsequent delivery. Further, the computer executes processing, using a VNC server, from failure occurrence until recovery. | 01-14-2010 |
20100091621 | Storage System and Communications Method - In a storage system including a host computer, and a disk control device connected to the host computer for communications therewith, and performs control over a disk device that stores therein data requested for writing from the host computer, for data transmission from a host interface section or a disk interface section to a memory section, when the data asked by a transmission source for storage is stored in a transmission destination, the transmission destination is put in a first mode for communications of forwarding a response back to the transmission source. With such a configuration, favorably provided is the storage system that offers a guarantee of reliability with the improved processing capabilities thereof. | 04-15-2010 |
20100100757 | POWER ESTIMATING METHOD AND COMPUTER SYSTEM - In order to calculate the power of logically-partitioned areas without using a power meter in a storage system logically partitioning a storage area, there is provided a power estimating method in a computer system including a management computer and a storage system connected to the management computer and a host computer. The storage system prepares logical storage-volumes in a real area of plural disk drives. The power estimating method includes the steps of: allowing a third processor to calculate operation rates of the disk drives for access to the logical storage-volumes from operating times of the disk drives for access to the logical storage-volumes; and allowing the third processor to calculate power consumption increments of the disk drives for access to the logical storage-volumes by access types from incremental power consumption information and the calculated operation rates of the disk drives. | 04-22-2010 |
20100306463 | STORAGE SYSTEM AND ITS CONTROLLING METHOD - This invention, in the interface coupled to the server, the disk interface coupled to the second memory to store final data, the cache to store data temporarily, and in the storage system with the MP which controls them, specifies the area by referring to the stored data, and makes the virtual memory area resident in the cache by using the storage system where the specified area is made resident in the cache. | 12-02-2010 |
20110004785 | STORAGE SYSTEM AND CONTROL METHOD OF STORAGE SYSTEM - A fault-tolerant storage system is provided. The storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies the failed component in the cutoff status, and invalidates the failed component. After invalidating the failed component, the storage system determines whether it is operable only with the normal components, cancels (releases) the cutoff of the I/O path when it determines that it is operable, and resumes operation by rebooting. | 01-06-2011 |
20110191520 | STORAGE SUBSYSTEM AND ITS DATA PROCESSING METHOD - The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor | 08-04-2011 |
20110231713 | FLASH MEMORY MODULE - Logical/physical conversion information is configured from first conversion information and second conversion information. A controller of a flash memory module restores the first conversion information at boot up time, enables an access command to be received from a host after having restored the first conversion information, and restores the second conversion information after an access command is able to be received. | 09-22-2011 |
20110238885 | STORAGE SUBSYSTEM - Processing in accordance with the updating of data is carried out distributively by a control unit that controls a cache memory and by a memory controller that controls a nonvolatile semiconductor memory. When updating flash memory data, a main processor creates an XOR write command and transfers the same to a flash memory controller, a microprocessor of the flash memory controller parses the XOR write command, reads out an old parity from a page of a user area in the flash memory, creates a new parity by carrying out an exclusive OR operation using the read-out old parity, “b” data, which is the old data, and “d” data, which is the new data, and stores the created new parity in a page of a renewal area in a flash memory for storing parity. | 09-29-2011 |
20110289277 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHODS AND PROGRAMS - The present invention obtains with high precision, in a storage system, the effect of additional installation or removal of cache memory, that is, the change of the cache hit rate and the performance of the storage system at that time. For achieving this, when executing normal cache control in the operational environment of the storage system, the cache hit rate when the cache memory capacity has changed is also obtained. Furthermore, with reference to the obtained cache hit rate, the peak performance of the storage system is obtained. Furthermore, with reference to the target performance, the cache memory and the number of disks and other resources that are additionally required are obtained. | 11-24-2011 |
20110296117 | STORAGE SUBSYSTEM AND ITS CONTROL METHOD - Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space. | 12-01-2011 |
20110296129 | DATA TRANSFER DEVICE AND METHOD OF CONTROLLING THE SAME - A data transfer device that confirms completion of writing into a memory on transferring data to the memory via a bus through which a response indicating completion of data writing in the memory is not sent back includes an inter-memory data transfer control unit performing data transfer between the memories. When the inter-memory data transfer control unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by a procedure different from writing into the memory. When a data transfer with a designated transfer length is completed, in order to confirm that writing is completed as to the write destination memory at the end of the data transfer, the inter-memory data transfer control unit performs confirmation of write completion as to the write destination memory at the end of the transfer by the procedure different from writing into the memory. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of write completion. | 12-01-2011 |
20110307721 | STORAGE APPARATUS AND POWER CONSUMPTION ESTIMATION METHOD - Proposed are a storage apparatus and a power consumption estimation method capable of easily and accurately estimating the power consumption of a physical drive without having to use a wattmeter. Operational information concerning a seek amount and a data transfer amount in the relevant hard disk drive which are internally recorded and retained by the respective hard disk drives is collected from each of the hard disk drives, and power consumption of each of the hard disk drives is estimated based on the acquired operational information of each of the hard disk drives. | 12-15-2011 |
20120005504 | STORAGE SYSTEM COMPRISING FUNCTION FOR REDUCING POWER CONSUMPTION - For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state. | 01-05-2012 |
20120059966 | STORAGE DEVICE AND METHOD FOR MANAGING SIZE OF STORAGE DEVICE - The invention relates to a storage device in which MR-IOV is applied to the internal network of a storage controller, whereby the size of the storage device can be easily expanded. The storage device is expanded on the basis of a network having processor-connected RPs, FE I/F, BE I/F, and CM I/F that are connected with a switch. In the switch, a plurality of ports other than those connected to the RPs, FE I/F, BE I/F, and CM I/F are connected with a cross-link. Each processor is allowed to control the FE I/F, BE I/F, or CM I/F either via a path that passes through the cross-link or via a path that does not pass through the cross-link within the unit device. When unit devices are connected to expand the size of a storage device, the cross-link is removed first and then the unit devices are connected with a new cross-link (see FIG. | 03-08-2012 |
20120096192 | STORAGE APPARATUS AND VIRTUAL PORT MIGRATION METHOD FOR STORAGE APPARATUS - The object of the present invention is to provide a technique in which, in a storage apparatus using a PCI Express switch in an internal network, an EP can be shared among processors even if the EP is incompatible with the MR-IOV. A storage apparatus according to the present invention is provided with a first interface device which controls data input/output to and from a higher-level apparatus, and the first interface device is further provided with multiple virtual function units which provide virtual ports. The first interface device enables any of the virtual function units and does not enable any of the other virtual function units (see FIG. | 04-19-2012 |
20120144252 | STORAGE CONTROL APPARATUS AND STORAGE CONTROL METHOD - A first memory area and a second memory area are provided. The first (second) memory area is provided with at least one first (second) memory module group, each of the first (second) memory module group is provided with at least one first (second) memory module, and each of the first (second) memory module is provided with a plurality of memory chip. In the case in which an error chip that is a memory chip that is provided with an error is in the first memory module, a first memory module group that is provided with the error chip is not managed as a memory module group that cannot be used even if there is a possibility that an error of the first data element is mis-corrected based on the error detecting code of the first kind. In the case in which an error chip is in the second memory module, a second memory module group that is provided with the error chip is not managed as a memory module group that cannot be used in such a manner that an error of the second data element is not mis-corrected based on the error detecting code of the second kind. | 06-07-2012 |
20120297244 | STORAGE SUBSYSTEM - The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data. | 11-22-2012 |
20120324162 | STORAGE SYSTEM COMPRISING FUNCTION FOR REDUCING POWER CONSUMPTION - For at least one of storage unit, processor and cache memory which are I/O process-participating devices related to I/O command process, when a load of one or more I/O process-participating devices or a part thereof is a low load equal to or less than a predetermined threshold value, a processing related to a state of one or more of the I/O process-participating devices or a part thereof is redirected to another one or more I/O process-participating devices or a part thereof, and the state of the one or more I/O process-participating devices or a part thereof is shifted to a power-saving state. | 12-20-2012 |
20130019123 | STORAGE SYSTEM AND COMMUNICATIONS METHOD - Storage system arrangement wherein: when a transmission destination determines that a source-side serial number included in a received packet is the same as a current destination-side serial number in the transmission destination, the transmission destination processes a content of the received packet in accordance with a command included in the received packet; and when the transmission destination determines that the source-side serial number is not the same as the current destination-side serial number, the transmission destination does not process a content of the received packet. | 01-17-2013 |
20130132656 | STORAGE SUBSYSTEM AND ITS DATA PROCESSING METHOD - The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor receives a write request from a host computer and data D | 05-23-2013 |
20130254487 | METHOD FOR ACCESSING MIRRORED SHARED MEMORIES AND STORAGE SUBSYSTEM USING METHOD FOR ACCESSING MIRRORED SHARED MEMORIES - According to a prior art storage subsystem, shared memories are mirrored in main memories of two processors providing redundancy. When the consistency of writing order of data is not ensured among mirrored shared memories, the processors must read only one of the mirrored shared memories to have the write order of the read data correspond among the two processors. As a result, upon reading data from the shared memories, it is necessary for a processor to read data from the main memory of the other processor, so that the overhead is increased compared to the case where the respective processors read their respective main memories. According to the storage subsystem of the present invention, a packet redirector having applied a non-transparent bridge enables to adopt a PCI Express multicast to the writing of data from the processor to the main memory, so that the order of writing data into the shared memories can be made consistent among the mirrored memories. As a result, data can be read from the shared memories speedily by accessing respective main memories in the respective processors. | 09-26-2013 |
20130275630 | DATA TRANSFER METHOD AND STORAGE SYSTEM ADOPTING DATA TRANSFER METHOD - According to a prior art data transfer method of a storage subsystem, when competition of data transfer accesses occurs, a free access destination port is allocated uniformly without determining the access type or the access state of the access destination, so that the performance of the device is not enhanced. The present invention solves the problem by selecting a data transfer access for completing data transfer with priority based on the access type or the remaining transfer data quantity of competing data transfer accesses, or by changing the access destination of an access standby data transfer access, thereby performing data transfer efficiently. | 10-17-2013 |
20130290281 | STORAGE APPARATUS AND DATA MANAGEMENT METHOD - The processing load when rewriting portions of compressed data is alleviated. | 10-31-2013 |
20130311706 | STORAGE SYSTEM AND METHOD OF CONTROLLING DATA TRANSFER IN STORAGE SYSTEM - An embodiment of the present invention is a storage system including a plurality of non-volatile storage devices for storing user data, and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host. The controller includes a processor core circuit, a processor cache, and a primary storage device including a cache area for temporarily storing user data. The processor core circuit ascertains contents of a command received from the host. The processor core circuit ascertains a retention storage device of data to be transferred in the storage system in operations responsive to the command. The processor core circuit determines whether to transfer the data via the processor cache in the storage system, based on a type of the command and the ascertained retention storage device. | 11-21-2013 |
20140104967 | INTER-MEMORY DATA TRANSFER CONTROL UNIT - A data transfer device that transfers data to a memory according to an instruction from a processor via a bus through which a response indicating completion of data writing in the memory is not sent back, comprises an inter-memory data transfer control unit including an operation start trigger receiving unit, a parameter acquiring unit, a read unit, and a write unit. When the write unit detects switching of a write destination memory, the write unit confirms write completion as to the memory by a procedure different from writing. When a data transfer instructed by the processor is completed, the write unit confirms write completion as to the write destination memory at the end of the data transfer by the procedure different from writing. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of the write completion. | 04-17-2014 |
20140115255 | STORAGE SYSTEM AND METHOD FOR CONTROLLING STORAGE SYSTEM - It is provided a storage system, comprising a storage device for storing data and at least one controller for controlling reading/writing of the data from/to the storage device. The at least one controller each includes a first cache memory for temporarily storing the data read from the storage device by file access, and a second cache memory for temporarily storing the data to be read/written from/to the storage device by block access. The processor reads the requested data from the storage device in the case where data requested by a file read request received from a host computer is not stored in the first cache memory, stores the data read from the storage device in the first cache memory without storing the data in the second cache memory, and transfers the data stored in the first cache memory to the host computer that has issued the file read request. | 04-24-2014 |
20140304461 | STORAGE SUBSYSTEM - The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data. | 10-09-2014 |