Patent application number | Description | Published |
20130275484 | DIVISION CIRCUIT AND MEMORY CONTROLLER - A separation circuit separates a 32-bit dividend, (e.g., 1695) into 4-bit segments and outputs 9 separated dividends. The position of each dividend counted from the dividend having the lowest bit is i. A first output circuit concatenates at the end of a dividend, 0s of number equal to an integer multiple of 4 bits. Each calculation circuit outputs an 8-bit quotient, a numerical value created by the first output circuit divided by 3(=2 | 10-17-2013 |
20130297895 | MEMORY CONTROLLER AND INFORMATION PROCESSING APPARATUS - A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data. | 11-07-2013 |
20130339591 | RELAYING APPARATUS, RELAY HISTORY RECORDING METHOD, AND DATA PROCESSING APPARATUS - When a relaying apparatus receives communication unit data transmitted from a processing apparatus that performs data processing, the relaying apparatus extracts preset data from the received communication unit data as trace information and calculates the number of pieces of the received communication unit data. History information of the received communication unit data is selected from the extracted trace information and statistical information obtained from the result of the calculation. The selected information is recorded in a storage apparatus available to the processing apparatus. | 12-19-2013 |
20140040680 | MEMORY CONTROL DEVICE AND CONTROL METHOD - A memory controller receives a read request and also issues a patrol request at a predetermined time interval so as to determine whether any error occurs in data stored in a DIMM. Furthermore, the memory controller generates a patrol address that is the subject of the subsequently issued patrol request. When the memory controller receives a read request, the memory controller compares the patrol address with the read address that is the subject of the received read request. When the read address matches the patrol address, the memory controller cancels the issuance of the subsequent patrol request. | 02-06-2014 |
20140304487 | INFORMATION PROCESSING APPARATUS, MEMORY CONTROL DEVICE, AND DATA TRANSFER CONTROL METHOD - A nonvolatile memory manages stored data by using physical addresses. By using logical addresses associated with the physical addresses, an arithmetic processing unit outputs a process instruction to be performed on data stored in the nonvolatile memory. On the basis of the process instruction output by the arithmetic processing unit, an access control unit detects an instruction to move the data stored in the nonvolatile memory. An address conversion table control unit stores therein the association relationship between the physical addresses and the logical addresses. When the access control unit detects the instruction to move the data, the address conversion table control unit changes the association relationship such that a logical address at the move destination is associated with the physical address in which the data is stored. | 10-09-2014 |
20140325123 | INFORMATION PROCESSING APPARATUS, CONTROL CIRCUIT, AND CONTROL METHOD - An information processing apparatus includes a cyclic frequency counter that updates a count value when a process that determines whether data stored in each of multiple storage areas included in NAND devices is targeted for a move has been executed on all pieces of data stored in the NAND devices. Furthermore, the information processing apparatus includes a table storing unit that stores therein, when data is stored in one of the NAND devices, the count value of the cyclic frequency counter associated with the data. Furthermore, the information processing apparatus includes a cyclic reference control unit that compares, for each data stored in the NAND devices, a value stored in the table storing unit with the count value of the cyclic frequency counter and then determines whether each piece of data is targeted for a move. | 10-30-2014 |
20140351628 | INFORMATION PROCESSING DEVICE, CONTROL CIRCUIT, COMPUTER-READABLE RECORDING MEDIUM FOR CONTROL PROGRAM, AND CONTROL METHOD - An information processing device includes: a storage device that has a plurality of storage areas; a detection unit that carries out error detection from read data out of the storage area belonging to the storage device; a readout unit that, in a case that the detection unit detects an error, identifies an area where error occurrence is estimated including a storage area in which the data where the error is detected is written and carries out readout of data individually from each storage area in the identified area; and a movement unit that, in a case of detecting an error from the data read out by the readout unit, moves the data to another storage area. | 11-27-2014 |
20140365809 | SEMICONDUCTOR CIRCUIT APPARATUS AND ELECTRONIC APPARATUS - A semiconductor circuit apparatus includes a controller configured to output a control signal, an outputting part configured to output the control signal outside of the semiconductor circuit apparatus, a condition holding part configured to hold a generating condition and an output condition of a trigger signal, a trigger signal generator configured to generate the trigger signal, if the control signal satisfies the generating condition, a delay controller configured to give a delay to the trigger signal based on the output condition, and a selector configured to be disposed between the controller and the outputting part and to selectively output the trigger signal delayed at the delay controller to the outputting part instead of the control signal output from the controller based on the output condition. | 12-11-2014 |
20140372673 | INFORMATION PROCESSING APPARATUS, CONTROL CIRCUIT, AND CONTROL METHOD - An information processing apparatus includes a storage device that includes a plurality of storage areas, and a processor coupled to the storage device. The processor executes a process including: first counting, among blocks each including a plurality of storage areas included in the storage device, number of transfer candidate blocks including the storage areas in which written data is invalidated; second counting, among the blocks, number of reserve blocks in which no data is written in the respective storage areas; determining whether transfer processing is to be started, in accordance with a result of comparing a count value of the first counting with a count value of the second counting; and transferring only valid data written in the respective storage areas of the transfer candidate block to the reserve block when it is determined that the transfer processing is to be started. | 12-18-2014 |
20140372675 | INFORMATION PROCESSING APPARATUS, CONTROL CIRCUIT, AND CONTROL METHOD - An information processing apparatus includes a storage device that includes a plurality of storage areas, and a processor coupled to the storage device. The processor executes a process comprising: selecting a logical address identifying data stored in the storage device; acquiring a physical address associated with the selected logical address, from a conversion table storing therein the logical addresses and physical addresses identifying the storage areas in which the data is stored in association with each other; determining whether the stored data indicated by the acquired physical address is to be transferred; transferring the stored data to another storage area when it is determined that the data is to be transferred; and updating the physical address associated with the selected logical address in the conversion table to the physical address indicating the other storage area. | 12-18-2014 |