Patent application number | Description | Published |
20080246091 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows. | 10-09-2008 |
20080246160 | STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire. | 10-09-2008 |
20090079087 | Semiconductor device and method for fabricating the same - A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern. | 03-26-2009 |
20110031536 | LAYOUT STRUCTURE OF STANDARD CELL, STANDARD CELL LIBRARY, AND LAYOUT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT - In a layout structure of a standard cell including off transistors | 02-10-2011 |
20110073953 | SEMICONDUCTOR INTEGRATED CIRCUIT - A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines. | 03-31-2011 |
20110079914 | STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire. | 04-07-2011 |
20110133253 | SEMICONDUCTOR DEVICE - A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G | 06-09-2011 |
20110284964 | SEMICONDUCTOR DEVICE - A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode. | 11-24-2011 |
20110298138 | STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire. | 12-08-2011 |
20120161241 | SEMICONDUCTOR DEVICE WITH DEVIATION COMPENSATION AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern. | 06-28-2012 |
20120168875 | SEMICONDUCTOR DEVICE - A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained. | 07-05-2012 |
20120292666 | SEMICONDUCTOR DEVICE - In end portions of first and second gate patterns aligned in parallel relation to each other, and opposite end portions of third and fourth gate patterns aligned in parallel relation to each other, the end portion of the first gate pattern extends to be positioned closer to the third and fourth gate patterns than the end portion of the second gate pattern is, and the opposite end portion of the fourth gate pattern extends to be positioned closer to the first and second gate patterns than the opposite end portion of the third gate pattern is. | 11-22-2012 |
20120306101 | SEMICONDUCTOR DEVICE - A power line structure is implemented which is capable of securing large interconnection resources for signal lines while suppressing a power supply voltage drop. Power supply potential lines and substrate potential lines are formed in a first wiring layer, and power supply strap lines are formed in a wiring layer that is located below the center of the overall height of the wiring layers. Upper via portions are arranged at a lower density in the direction in which the power supply strap lines extend than lower via portions. | 12-06-2012 |
20130113112 | SEMICONDUCTOR DEVICE - A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect. | 05-09-2013 |
20130154009 | SEMICONDUCTOR DEVICE - A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode. | 06-20-2013 |
20130234211 | SEMICONDUCTOR DEVICE - A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G | 09-12-2013 |
20140077307 | SEMICONDUCTOR DEVICE - A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode. | 03-20-2014 |
20140159160 | SEMICONDUCTOR DEVICE - A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained. | 06-12-2014 |
20140252653 | LAYOUT STRUCTURE OF STANDARD CELL, STANDARD CELL LIBRARY, AND LAYOUT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT - In a layout structure of a standard cell including off transistors | 09-11-2014 |
20150014781 | SEMICONDUCTOR DEVICE - A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring. | 01-15-2015 |